Design-optimization And Verification Of BP Component And Shuffle Unit In X-DSP

X-DSP is a 64-bit multi-core processor with high performance, whose kernel adopts 11 emission VLIW(Very Long Instruction Word) structure. The frequency of X-DSP is 1.25 GHz. In the DSP core, the BP(Bit-Processing) component and the Shuffle unit are set independently. BP is the digital processing units in DSP core, which supports the bit processing operations of fixed-point arithmetic for the entire chip. All instructions of the BP components are single-cycle. Therefore, it is a big chanllenge to design a BP component of high performance. The Shuffle unit is located in Vector Processing Unit(VPU). It realizes the data interaction among VPEs registers. It is crucial to the whole DSP’s performance. This study investigates and completes the design, verification, optimization and synthesis of BP components and Shuffle unit.1. According to the X-DSP design requirements, the BP component instructions and micro-architecture of SIMD(Single Instruction stream Multiple Data streams)rchitecture with 32/64 bits are designed. A shifter with two modes is designed based on the switch selection technology. A mask shifter is also designed through the thardware resource multiplexing technique. The instructions of BCLR、BSET、BEX、BTST are realized based on the hardware structure of multiplexing shift logic.2. Two different kinds of instructions are designed to support Shuffle mode, which is immediate or SMR In order to improve the performance of Shuffle, shuffling pattern memory is adoptted independently.Which independent configuration path and execution path, aim at separating decoding and execution.3. The BP components and Shuffle unit are synthesized and their critical path is optimized. The optimization of BP unit is realized by adoptting logic reused technology and structure adjustment method. We change serial shift into parallel shift to optimize the critical path of BEXT instruction. The pipelined technique and increasing memory stores is used in Shuffle unit to optimize the configuration path. The DC results demonstrate that the dynamic power decreased by 24.84% and the area decreased by 96064 um2.4. The BP components and Shuffle unit are verified by simulation verification and formal verification methods. Firstly, the gold model is constructed for BP components and Shuffle unit. The model is used for the results comparison in functional verification, and as the reference model for formal verification. Secondly, pseudo random number is devoloped to test stimulus. At last, by using the equivalence checking tool(ATEC), the design and the gold model are proved to be completely equivalent. Using Formality tool, the coherence between the gate-netlist and the RTL codes is checked and compared.