Improvement Method Study Of Microprocessor I/O Protection Circuit Under Transient Pulse Interference

With the development of IC industry and manufacturing technologies steadily improving, microprocessor characteristic size has developed to nanometer level. As the working environment becoming increasingly complex, Electromagnetic Compatibility(EMC) of transient pulse becomes a serious problem. Especially, as one of the most important EMC problems, ESD has become a key factor affecting the reliability of the microprocessor. Based on a Power-up ESD(PESD) test platform, the impact of PESD pulse on microprocessor I/O protection circuit has been studied in this paper. A microprocessor I/O protection circuit design idea is put forward in this paper, that preventing turn on latch-up to improve the microprocessor’s reliability, emphatically analyze the latch-up mechanism. Finally, this paper put forward two specific microprocessor I/O protection circuit designs, and verifies the improved design method by comparing the first and second-generation microprocessors PESD test results.In the first part of the thesis, the microprocessor I/O protection circuit structure is studied. In the first step, this part research the microprocessor I/O protection circuit design principles, and analyze the key factors of the ESD protection design. Then three typical microprocessor I/O protection circuits are specifically studied, including their advantages and disadvantages. Trigger circuit which is the critical structure of microprocessor I/O protection circuit is depth researched. The main strategies and important parameters in the trigger circuit design are analyzed; two common trigger circuit structures are mainly studied.In the second part of the thesis, the microprocessor I/O protection circuit’s test methods are studied under transient pulse interference. In the first step, comparing several ESD test parameter, this peper analyze the PESD test method. In the second step, the PESD test platform design and implementation are studied. PESD test environment setup, test board and test code are mainly analyzed. Test results are summarized to obtain the impact of PESD pulse on microprocessor I/O protection circuits.In the third part of the thesis, the improved method of microprocessor I/O protection circuit on PESD test is researched. The latch-up is the important factor that affects the microprocessor I/O protection circuit’s reliability by analyzing the PESD test result. This paper put forward a microprocessor I/O protection circuit design ideas that preventing latch-up generation to improve the PESD performance. Then the mechanism of latch-up is deeply analyzed. Finally, two methods that improved microprocessor I/O protection performance are put forward and verified by comparing the first and second-generation microprocessors PESD test results.