Scan Clock Grouping Method Based On Randomized Clustering Algorithm

At present, So C design methodology based on IP(Intellectual Property) reuse makes ASIC(Application Specific Integrated Circuit) design more efficient. But this method also brings some new challenges, testability(DFT, Design For Testability) of the high performance integrated circuits is the most serious part.The main subject is to achieve an optimal ATPG scan clock structure of a large-scale digital baseband chip containing synchronous and asynchronous clock domains. For the test of large scale chips, it is difficult to achieve high fault coverage.We take the ATPG clock structure of a digital baseband chip as the research object, in order to improve the fault coverage and reduce the test patterns, randomized clustering algorithm is applied to generate the scan clock structure. Then we use improved staggered LOC technology to generate test patterns. The main research contents and achievements are as follows:1. In those clustering algorithms, hierarchical clustering algorithm is fast and simple, but its precision is low. We introduce the randomization step in the hierarchical clustering algorithm, then the algorithm contains some random component. After several operations, we can select the optimal result to make up for its low precision, making it suitable for chip clock domain grouping.2. In stuck-at test mode, using randomized clustering algorithm to group clock domains, we can get optimized scan clock structure, the number of propagation path which crossing clock domains will be reduced, and the fault coverage of stuck-at test will be improved.3. In delay test mode, using randomized clustering algorithm to group clock domains. Then we use simultaneous Launch-on-Capture and improved staggered capture technology in the same capture window, perform parallel test for clock domains within the same group, serial test for different groups. Test time and the number of patterns have been reduced.