The Design And Verification Of Multiplier Applied To The Powerpc Processor

The multiplier is one of the important operational components in the PowerPC processor chip. Because there is a long delay in traditional multiplier, it often becomes bottleneck of system. Therefore, a high-performance multiplier is designed in this paper to provide hardware acceleration for the PowerPC processor chip which basic frequency is 400MHz.Through in-depth understanding of the multiplier principle and algorithm, the multiplier is divided into three modules which are partial product generation module, partial product compression module and final summation module. In this thesis, the modular circuit of multiplier is optimized. In the partial product generation, the radix-4 Booth algorithm and the selector is used to generate the partial product and the selector is composed of the transmission gate. The delay time of Booth algorithm circuit is significantly reduced. In partial product compression, the high-performance 4:2 compressor and 3:2 compressor is used. The compressor is composed of highly symmetrical XNOR structure and selector. The delay time of the compressor is very small. At the same time, the output of the compressor has been well balanced. In the final summation stage, the lookahead carry adder, which has the advantage of the parallelism of carry between groups and within groups, is used. In the implementation of the multiplier, the pipeline technology is used to improve the maximum operation frequency of the multiplier.The module level and system level simulation is completed. SMIC 0.18μm process is used for post simulation. Experimental results show that the function of the multiplier is correct and the longer delay time in two-stage pipeline is 1.364ns which can work in 400MHz processor. The results show that the multiplier meets the requirement.