Font Size: a A A

Research On DSP And FPGA Based Signal Processing Module And Related IP Core Design Technology

Posted on:2017-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:Q MaoFull Text:PDF
GTID:2308330485457127Subject:Electronic information technology and instrumentation
Abstract/Summary:PDF Full Text Request
With continuous expansion of digital signal processing applications and the further development of digital signal processing technology, the performance requirement of digital signal processing enhances unceasingly, a simple system composed by DSP often cannot meet the critical real-time requirement of high-performance computing. By using DSP and FPGA co-processing architecture can play to the advantages of both, effectively improve system computing performance, reduce system power consumption, and has important engineering application value.This thesis discusses DSP and FPGA co-processing architecture and design technology of several communication and computing IP cores in FPGA, and completed the hardware circuit of signal processing module based on multi-core DSP and high-capacity FPGA. In the FPGA project achitecture based on an interconnector IP core, this thesis does research on customizable universal standard bus interface of IP core using AXI4-Stream protocol, designes and realizes a number of communication interface IP cores and high-performance computing IP cores, including SRIO interface IP core and covariance computing IP core. SRIO interface IP core uses multi-level data cache structure, support multiple kinds of I/O transactions, data classification, data flow control; covariance computing IP core uses massively parallel architecture to achieve a rapid calculation, and it can be configured with several parameters to improve IP core reusability.Through experimental verification, DSP and FPGA co-processing hardware architecture is feasible, design is correct, meets the high system throughput and processing requirements. Through tests, SRIO interface IP core can send and receive data correctly, stably and rapidly, and the data transmission speed is up to 1.76GB/s, 88% of the theoretical value; The time covariance computing IP core need to calculate a covariance matrix of 108 x 108 size is only 334.3us, compare with the DSP computing time, the computation speedup rate is up to dozens of times, apparently improved the capable of real-time processing of signal processing system.
Keywords/Search Tags:DSP, FPGA, IP core designing, SRIO protocol, covariance calculation
PDF Full Text Request
Related items