Universal Verification Methodology Study And Its Application To Design Modules Of DVLINK Chip

With the rapid development of deep sub-micron semiconductor technology and ultra large scale integrated circuit design, ICs become more and more powerful. The high integration requirement brings increasing challenge to the digital IC. In the R&D process of the digital IC, most of the work is devoted to its verification, which has always been an important issue in the industry. Meanwhile, verification methods and forms have been further innovated.The project is mainly to study a verification methodology-UVM (Universal Verification Methodology), based on a project of a company. Verification platform is firstly built up, and the high-definition image transmission chip (DVLINK) modules are chosen for verification. After that, the function test points are refined, and the functional verification is accomplished by coverage-oriented methodology for the entire module verification process. This work also aimed at the system-level model testing, further study model checking methods will provide a testing method for the development of VLSI testing. Details are as follows:Before verification is carried out, communicate with the module design team, combined with the module design specifications, analyzed the detailed function of DVLINK, and analyzed its performance requirements, etc., and also involved in part of the module design, considered full the each module design specifications in the project. Depending on the design requirements of different module code, extract various test points, and using Black-box Verification, Grey-box Verification and other testing programs, and draw up verification goals, and verification plan for the entire project.Secondly, the UVM verification platform construction is discussed. According to the set-up norms of the UVM verification platform, the study uses the "top-down" method, and combines with System Verilog language for hierarchical components description, builds verification platform through the transaction-level modeling. UVM verification platform provides a scalable and repeatable verification environment, combined with the design specification of modules to build reusable verificationFinally, simulating by Synopsys’ VCS, analyze the coverage for further optimization. This work also discusses the further study of system-level test point, modules testing provides a means of testing for VLSI. In the stage of simulation, the verification platform, which is endowed with modular-design,and expandability, provides the flexibility for module building, time-saving and efficiency improvement.