The Research And Implementation Of Key Technology For Clock Gating Auto-Optimization On 40Gbps High Speed Serial Interface Controller

Traditional synthesis tools have the ability to identify and insert combinational clock gate elements into circuit automatically. However, greater dynamic power consumed by registers and its downstream logic can be saved through sequential clock gating optimization. Until recently, sequential clock gating requires manual identification and implementation by experienced hardware designers,they have to decide which register could be enabled and when they are working through sequential analysis. This manual method is difficult and error-prone. Therefore, it is necessary and important to propose the concept of Clock Gating Auto-Optimization. This paper does research into sequential analysis technique of cross-registers circuit and key technology for sequential Clock Gating Auto-Optimization, and apply it to 40 Gbps Interface Controller so that to reduce dynamic power consumption as much as possible. In brief, this dissertation mainly includes the following content:1. Does deep research into sequential analysis technique of cross-registers circuit and key technology for sequential clock gating auto-optimization. Gave a detailed introduction on two sequential clock gating auto-optimization methods, Observability Based Sequential Clock-Gating(OBS) and Input Stability Based Sequential Clock-Gating(STB) respectively. At the same time, a metric used to measure the effectiveness of clock gating is introduced, that is Clock Gating Efficiency. Also, we describes how to automate the sequential analysis, and power/timing/area tradeoffs to choose the optimal solution.2. In the rest of our research, we applied the previous proposed Clock Gating Auto-Optimization technique to 40 Gbps High Speed Serial Interface Controller. And does a detailed comparison of the percentage of clock-gated registers and clock gating efficiency between optimized design and the original one. In order to verify the functional correctness of optimized design, the equivalence check and fuction simulation also be done using SLEC and VCS respectively.3. Analyze and compare the timing, area and density results after the backend implementation state including synthsis, place & route and CTS. By post-layout power estimation on 40 Gbps High Speed Serial Interface Controller using Cadense EPS power analysis tool, we have obtained on average, 23.92%, actual power reduction compare with the original design on the premise that no performance degradation.