Design And Implement Of Cascaded Digital Filter In Delta Sigma ADC

In recent years, Delta-Sigma ADC has been widely used because of its good performance. The analog moodulator uses oversampling and noise shaping technology, so noise is modulated to a high frequency, which greatly reduces the noise level within the band. Thereby increasing the signal to noise ratio. In order to filter out the modulated high-frequency noise outside the passband, the digital filter is very important. Since the digital filter in the entire ADC occupies a major area. Therefore, to reduce the cost of digital filter’s hardware has become a major research directions.The cascade digital filter in Delta-Sigma ADC was designed in HHNEC 0.5 μm Process. Cascade digital filter is consisted of the CIC(cascade integrator comb) filter, CIC compensation filter and two half-band filters. CIC filter is placed in the first stage of sampling rate is relatively high, which is conductive to get a better stop band attenuation and less prone to aliasing. Because of the attenuation of its magnitude in pass-band, the second stage uses a CIC compensation filter to compensate the attenuation in the pass band. Last stage uses the half-band filter because it has a narrow band, flat pass band and flat stop band. CIC filter uses an improved structure of a direct down-sampling. CIC compensation filter uses the structure of SOPI(second order polynomial interpolation). And the half-band filter uses a structure which is consisted of prototype filter and sub filter.In order to reduce hardware costs, in addition to the advantage of the filter structure, the adders and coefficient also been careful handling. Coefficient processing using CSD code will convert multiplication to shift summation, which can reduce hardware costs. Using a dedicated adder instead of the common adder can reduce the number of bits of register, and then reduces the hardware costs.Behavioral modeling and simulation, register transformation level coding and simulation, design compiler synthesis, automatic placement and routing, static timing analysis and post-simulation have been conducted in order to implement a better cascade digital filter. Finally, based on the DISLIN3 project, integrate the layout of analog modulator and digital filter and IO layout. The sampling frequency is 6.144 MHz, down sampling rate is 64, the Nyquist bandwidth is 96 KHz, pass band cutoff frequency is 44 KHz, stop band cutoff frequency is 52 KHz. Finally, the SNR is 105.7 dB and area is 24455×4455μm~2.