Design Of Image Data Transmission System Based On PCIE Bus

Space camera is an important kind of remote sensor in the field of space exploration, which includes aerospace surveillance cameras, aerospace mapping cameras, and so on. Besides, it is also widely used in civilian and military fields. When test the performance of aerospace camera, the large amounts of image data need to be transmitted to computer rapidly and reliably, which puts forward a higher requirements for the computer system bus. As the third generation of system bus, PCIE bus has been used more and more often in the occasion where needs high-speed data transmission because of its high bandwidth, new point to point interconnect architecture and compatibility with PCI bus. In order to test the performance of space camera, this paper designs an image transmission system based on the PCIE bus.Altera Cyclone IV FPGA is the control center of the transmission system, which can fulfill the PCIE interface circuit by its internal IP core. The LVDS image data can be transferred into the single-ended signals by the LVDS interface chips, then enter FPGA after the isolation circuits. In order to receive data in real time, two RAMs are customized in FPGA. FPGA will transmit data to the computer rapidly using DMA mode when certain condition is satisfied, and the image can be displayed in computer.The paper designs an image data transmission system based on the PCIE bus after the technical requirements are analyzed in detail, then elaborates the composition, the principle and the function of each part.The design mainly contains two parts, hardware design and FPGA logic design. The former includes LVDS interface circuit, FPGA configuration circuit, power supply circuit and isolation circuit. The FPGA logic design mainly achieves two goals: the first is buffering the image data received, which can be achieved by the ping-pong operation of two RAMs customized in FPGA. The second is fulfilling the PCIE interface circuit, which can be achieved by customizing PCIE IP core and editing the program generated by it.The test of the system mainly includes two parts: tests of FPGA internal logic design and real effect of the system. The results show that this system is reliable.