Design Of LVDS Serial Interface Transmitter Based On 28 Nm CMOS Process

At present,China’s industry of new energy automobile has entered the expansion period of comprehensive market-oriented,and is gradually moving towards the goal of full-link digitalization and intelligence.The main function of the data transmitter interface chips is to realize the data transmission between different IC modules,data transmitter interface chips are widely used in auto parts such as automotive dashboards,head-up displays and image sensors,Therefore,studying a LVDS interface chip with high performance is extremely important for the digitalization and intelligence of China’s new energy automobile.The development and research of low voltage differential signal(LVDS)technology is introduced by this thesis,and the principles of LVDS technology and LVDS interface driver’s standard specifications of TIA/EIA-644-A standard which is widely used is explained.On this basis,a LVDS transmitter circuit is designed that can be used for automobile instrument panels,head-up display,etc.This LVDS transmitter circuit mainly includes functional sub-modules such as phase locked loop,parallel-to-serial conversion circuit,LVDS driver,reference sources and so on.The charge pump in the phase locked loop uses a full differential structure,and the three-transistor switch structure is proposed to reduce the non-ideal effects such as the clock feeding effect,which can effectively suppress the jitter of the multi-phase clock generated by the phase locked loop.The parallel-to-serial conversion circuit uses a multi-phase clock structure,so that the operating frequency of the conversion circuit is the same as the frequency of parallel data signals,which effectively reduces the power consumption of the overall circuit.The current flowing through the terminal resistance and output signals of LVDS driver are more stable with the application of dual-current source and common-mode feedback circuit.The reference sources use the low-voltage bandgap reference structure to achieve the purpose of working under low power supply voltage.This thesis uses 28 nm CMOS process to complete the design of the circuit schematic and layout of the LVDS transmitter,and perform verification and analysis of simulation.The results of the simulation experiments show that the LVDS transmitter can work normally with different conditions of PVT.The frequency of parallel input data is from 25 MHz to 152 MHz,the serial output signal with frequency of 175 MHz～1064 MHz meets the LVDS standard.When the output frequency is1064 MHz and the load capacitance is 10 p F,the output common-mode voltage can be stabilized at about 1.25 V,the output differential mode voltage ranges from 277 m V to 398 m V,and the rising and falling delay time of output signal are less than 0.3UI.