Design Of A Low Noise LDO Integrated In RF Chip

LDO(low drop regulator)is one of power manager schemes with many outstanding parameter in analog circuit designs such as lower noise performance,higher power supply rejection ratio,lower power performance,better linear adjustment rate and more fast transient response.Nowadays LDO has been widely used in many fields,such as the portable mobile electronic equipment,the wearable electronic products,internet of things and so on.With the rapid development of RF chip,LDO has been widely used in the field of RF chips.LDO can provide a low noise,low power consumption stable voltage for RF chip without the RF interference.This is also the current development trend of all integrated RF chips.In this paper,the design of LDO is based on SMIC 0.18?m CMOS Technology.It is a low dropout linear regulator integrated into RF system.This paper begins with the introduction of the main performance parameters of LDO.Then,the circuit structure of LDO is proposed,and three main aspects are designed from the bandgap reference voltage source,error amplifier and protection circuit.In theory,the noise and stability of LDO are analyzed in detail.And this basis,the system use Miller compensation circuits to ensure the stability of LDO.In the design of LDO,it has the advantages of low quiescent current,high power supply rejection ratio and high load transient response.In addition,in order to ensure the stability of the circuit,the circuit also increases the overvoltage protection circuit,short circuit protection circuit and overheat protection circuit.After the completion of the circuit design,the simulation of the whole circuit and each sub module is verified by H-spice simulation platform,and complete the layout design of LDO.Through the simulation results of H-spice,we can see that the LDO parameters have achieved the desired objectives.Simulation results show that quiescent current is 47.1?A and load regulation is 0.003%.