Research And Design Of Capacitor-free Low-dropout Voltage Regulator

The conventional low-dropout regulator(LDO)require large values of output capacitance to ensure the system stability.But it exists two major issues: first,the position of the pole produced at the output is not fixed,but varies with the load impedance,LDO-compensation schemes are critically load-dependent.So,the values and the types of the output capacitor are strictly disciplined.Moreover,the output capacitor increases the cost and the area of the PCB board,which is contrary to the direction of the electronic integration.So,it is essential to study the capacitor-free LDO.This paper,at first,introduced current s tatus and development trend of power management IC and LDO,and expounds its work principle,as well as several methods to improve the stability and transient response of the system.Then,the design idea of the circuit structure of a capacitor-free LDO is presented detailedly,meanwhile,the design and simulation of the sub-circuit of system are followed.Finally,the simulation of the whole circuit is given to verify the design specification and function.In this paper,the capacitor-free LDO regulator uses NMOS as the power transistor,the DC bias of the power transistor's gate is controlled by the servo transconductance amplifier circuit and the capacitor,the voltage generated by a low current charge pump circuit is used as the supply voltage of the servo transconductance amplifier circuit,with this approach,the gate voltage of the power transistor is boosted,and the ripple effect on the output voltage is reduced.Meanwhile,the variable reference voltage circuit is used to increase the output swing of the error amplifier,so the dynamic range of the voltage regulator is improved.Also,the stability of the DC operating point of the system is improved by the servo transconductance amplifier and capacitor.The design and simulation were completed with Cadence platform and Hspice D software based on the 0.35?m CMOS process.The simulation results show that the chip with following characteristics: the dropout voltage is approximately 100 m V,the worst phase margin of the system is approximately 45°.Within all temperature range,the temperature coefficient is 14.108ppm/°C,and the output is steady within all load range and all input voltage range.In conclusion,the function and performance of the capacitor-less LDOdesigned in this paper meets the design specification.