Based On Pseudo Continuous Regulation Mode For Design Of Low Ripple And High Efficiency Voltage Doubler Charge Pump

In recent years,switched capacitor DC-DC has become more and more widely used.As NAND flash memory is widely used in smart phones,PCs and other electronic devices,the density of NAND flash memory arrays is getting higher and higher.Therefore,the output load of the high-voltage generator mainly comes from the capacitance of the word line(WLs),and the capacitance of the word line increases dramatically makes the design of high-voltage generators face huge challenges.In order to reduce the interference between WLs and improve the accuracy of the threshold distribution,the output voltage ripple of the charge pump in NAND flash memory must be reduced.At the same time,since the power consumption in NAND mainly comes from the charge pump,the low power consumption design of the charge pump must be considered.This paper designs a switched capacitor voltage doubler based on pseudo continuous regulation mode(PCC),which has a smaller output voltage ripple and high efficiency.The PCC switched capacitor voltage doubler uses dual-loop alternating control to continuously adjust the output voltage,which reduces the output voltage ripple compared to discontinuous output regulation;the PCC switched capacitor voltage doubler does not require additional power transistors to continuously adjust the voltage doubler output,which saves chip area;the PCC switched capacitor voltage doubler also uses a three-stage amplifier to obtain a large loop gain and improve the loop response.In order to ensure loop stability under high loop gain,the three-stage amplifier uses Active feedback frequency compensation(AFFC),and in order to reduce the size of the compensation capacitor,damping factor control technology(DFC)is used.The adopted PCC control mode can effectively control the maximum output voltage ripple due to the fast loop response.The PCC control method not only improves the speed of the loop response,but also improves the load transient response of the voltage regulator multiplier.Since the PCC switched capacitor voltage doubler is continuously controlled by a three-stage amplifier,the loop response of the PCC switched capacitor voltage doubler is independent of the switching frequency,thus allowing the voltage doubler to operate at a lower switching frequency without sacrificing transient response.The light-load efficiency of the voltage regulator multiplier can be improved by reducing the switching frequency and reducing the switching power loss.The voltage doubler also uses a break-before-make mechanism to minimize the shoot-through current,thereby greatly reducing the no-load power supply current dissipation and improving the light load power efficiency of the voltage doubler.In addition,by adopting the gate slope reduction technique during the turn-on of the power transistor,the switching noise of the voltage doubler can be greatly reduced.Switched capacitor voltage doubler based on PCC control has been designed and simulated in 0.18μm GSMC CMOS process.The voltage doubler maintains a maximum output voltage ripple of 15 m V when the load current changes from 50 m A to 150 m A when the 2.2 μF output capacitor is used at a switching frequency of 200 k Hz.Compared with the voltage doubler charge pump(output voltage ripple of 30 m V)using 0.18μm TSMC CMOS technology combined with transition and linear mode,the output voltage ripple of the voltage doubler charge pump designed in this paper is reduced by 50%.In this paper,the maximum efficiency of the switched capacitor voltage doubler reaches 90%,and the transient recovery time of the voltage doubler is about 30μs when the load current step change is 100 mA/1μs.