The Research And Design For High Performance Switched Capacitor DC-DC Converters

As the development of electronic technology, power management technology is widely applied to different electric systems. And among them, the DC-DC converters have the widest applications.The DC-DC converters can be divided into three types: low drop-out (LDO) linear regulator, switched inductance DC-DC converters and switched capacitor DC-DC converters (Charge pump). Among them, switched capacitor DC-DC converters have got wide applications in portable products and small and medium-power areas due to their high efficiency, small EMI and small size. Therefore, in this thesis the switched capacitor DC-DC converters have been thoroughly studied. To adapt to different applications, switched capacitor DC-DC converters are divided to single and multi-stage. Both of them were analyzed in this thesis and the corresponding designs were proposed and completed by authors.As to single stage switched capacitor DC-DC converters, this thesis proposed a novel charge pump system based on variable frequency modulation (VFM). By adjusting the clock frequency automatically, the system could provide stable output with high efficiency and low ripple over a wide range of load current. The single stage system was designed and realized in TSMC 0.35um mixed-signal CMOS process with the die size of 1.5mm×1.5mm. The simulation and test results showed that the design goals have been achieved. The control strategy of the load adjusting frequency, the shortcomings of traditional control strategies were overcome and low ripple output as well as high efficiency was achieved for converters.And as for multi-stage ones, an on-chip multi-stage system fabricated with standard single well process was proposed, which is features low cost, high efficiency and larger current driver capacity. To meet the demands of the system, a cross-coupled full PMOS structure of step-up unit was introduced. And through modeling the multi-stage system, the current driver capacity and efficiency of the system was analyzed. Based on it, a three-stage system is simulated and designed in TSMC 0.35um mixed-signal CMOS process using Spectre of Cadence. The simulation results showed that the expected goals have been achieved. The three-stage system in standard single well process is capable of avoiding the inner high voltage impact and made the average gain per stage as high as 96% or more of Vdd.