Research On Hardware Acceleration Of Connected-component Labeling Algorithm Based On High-level Synthesis Method

In missile-borne imaging home guidance system,rapid image processing including target detection,segmentation and connected-component labeling are highly demanded.However,the real-time collected image sequence produces large data amount which is time-consuming when traditional method involved.Consequently,this will highly affect the subsequent tracking and recognition tasks.Thus makes it significant to adopt a rapid connected-component labeling algorithm for resolving the systematic restriction problem.The research is focused on hardware acceleration based connected-component labeling algorithm.Simultaneously,due to the deficiency of traditional hardware circuit design,the method based on high-level synthesis is made for the research of hardware acceleration based connected-component labeling algorithm.The main research details are as following.Most rapid connected-component labeling algorithms perform excellently in popular platforms while has poor performance in missile-borne guidance target tracking system,more exactly is unsatisfied for real-time need.In order to solve this problem,based on the analysis of different connected-component labeling algorithms,an improved label-equivalence-based two-scan algorithm based on two-level tree structure is proposed.The proposed algorithm preponderates in parallel framework and has an adaptive framework in pipeline processing which is convenient in hardware acceleration.Traditional hardware circuit design possesses lots of problems.It comprises numerous manual steps which are time consuming and delay systematic period.Also,it is difficult to revise which may easily leads to a sub-optimal design.Additionally,the gap between system design area and hardware design area promises relatively big fluctuation in circuit function.Therefore,the thesis adopts the method based on high-level synthesis tools to design the hardware circuit.Through the research on high-level synthesis tool,Catapult C,the design regulations of how to compose synthesizable C/C++ code and to generate RTL code are concluded.By C synthesis of proposed connected-component labeling algorithm and the simulation and synthesis of generated RTL code,the consistency of algorithm transformation is verified.The experimental result shows that the proposed algorithm has less resource cost but the real-time ability needs to be developed.Aiming at better performance in projecting connected-component labeling algorithm to hardware,the algorithm projection space is explored through the research on high-level synthesis.By reducing the read and write times of memories,pipeline processing and row cache,an optimization design is achieved.The timing simulation and logical synthesis for generated RTL code is accepted and the experimental result shows that the hardware circuit design decreases the time delay through the optimization,and the highest clock frequency increases from 100 MHz to 133 MHz after synthesis.The design performance is further elevated.