Research And Design Of Data Transmission System Based On CPCI Architecture

The wideband data link of UAV is the data transmission channel of mission payload,and the important component of UAV system,of which the performance directly affects the overall performance of UAV system.As the performance of UAV improves constantly,the category and complexity of airborne equipment are increasing continuously,the data processing and transmission capability of UAV telemetry&control system will largely determine the performance and scale of the entire UAV system.Therefore,it is required to improve the data processing and transmission capability of UAV telemetry&control system constantly.For the above requirements,the paper studies a data processing terminal in detail,which takes CPCI bus technology as core foundation,collects multichannel data generated simultaneously by multiple TT&C links into the computer through CPCI bus in real time,and provides well stability and data processing ability to communication receiving system.On the basis of this scheme design,the paper implements a common CPCI signal processing hardware platform based on software radio(SR).At first,the paper analyzes the features of CPCI bus criterion and the advantages and applications of CPCI bus standard,elaborates the purpose and significance of the research of common hardware architecture paltform based on CPCI,describes the research background and engineering requirements of this project,and introduces the main work of this project design:according to the technical characterstics of CPCI bus,it designs an open,normalized and modular common hardware platform for data transmission.Secondly it analyzes the system functions,performance requirements and technical requirements of SR CPCI signal processing platform,determines the system platform,system architechture,design scheme and implementation principles according to the system functions and characteristics of terminal processing platform,allocates hardware module and board division and detailed design,and plans the design details of platform internal buses and each modules.And then,it analyzes the overall system architecture,system requirements and detailed modular requirements aiming at the overall design scheme of system CPCI high speed data transmission,and selects the key chips.It selects the hardware circuit based onDSP+FPGA architecture,designs the external memory and the dependent auxiliary circuit around the architecture,analyzes the parameters in terms of the signal flow and concrete implementation,reasonably selects the specific type of the core chip and implements the functional partition and design optimization on the basis of the selection results.It also introduces the logic design of system software and the composition,detailed design and implementation of the hardware modules.In addition,it introduces the hierarchical structure of the software and hardware in detail,and implements the system software design.It mainly includes programming of DSP,FPGA logic programming,elaberating the data flow transmission between DSP and FPGA,program development of data transmission between DSP and CPCI bus,interface interaction,implementing the data interconnection and interworking of the PCI interface bus based on DSP and the host and each functional unit.FPGA or DSP loading program implements board online loading from PC file system through CPCI bus to realize the board function reconstruction.Finally,it implements the test and verification analysis of the designed data processing terminal platform.The test program receives the bus data and implements the functions such as data statistics,error code comparison,data storage and updating test program online.Processing the transmission and receiving data,and decompression and display the image on IPC,the image quality is good,there is no error code phenomenon such as blurred screen caused by data packet dropout.The test validates that the processing capability of data receiving equipment meets the engineering requirements of transmission rate and real-time,and the online loading function of CPCI bus program.