Hardware Design Of Data Acquisition System For 20GSPS Digital Oscilloscope

With the rapid development of electronic information technology,the electrical signals show a highly complex trend of change.In view of the capture and analysis of high frequency and transient signals,a data acquisition system with higher bandwidth and higher sampling rate is needed.As one of the core indexes of the digital oscilloscope,the sampling rate,to a great extent,represents the capture ability of the complex signal.There are two ways to improve the sampling rate of digital oscilloscope.One is to improve the performance of Analog to Digital Converter(ADC),and the other is to use Timeinterleaved ADC(TIADC)technology to break through the performance bottleneck of single ADC.The foreign mainstream oscilloscope manufacturers significantly improve the sampling rate index through the above two ways,and launched the product of digital oscilloscope with ultra-high sampling rate.Due to the limitation of the ADC chip performance,it is difficult to improve the performance of the data acquisition system by improving the sampling rate of single ADC.Under this background,this paper studied the parallel architecture of ultra-high-speed data acquisition system and the problem of synchronization between multiple ADC and multiple FPGA,designed the hardware platform of data acquisition system for dual channel 20 GSPS digital oscilloscope.Main indicators: the maximum real-time sampling rate of dual channel 20 GSPS or four channel 10 GSPS,and the vertical resolution of 8 bit.The specific research contents of this paper are as follows:1 ? According to the structure and basic principle of ultra-high speed parallel sampling system,the data acquisition system of a dual channel 20 GSPS digital oscilloscope is constructed by using 8 pieces of 5GSPS ADC and 9 pieces of FPGA through the in-depth analysis of the parallel architecture of the ultra-high speed sampling system,including the module of broadband signal multiplex drive,the sampling array with multi ADC,the data processing array with multi FPGA,high speed trigger circuit,power supply system and so on.2?The production of low jitter multi-phase sampling clock and the design of ADC reset circuit based on high-precision retarder.Based on the modular design of multi-channel high-speed data acquisition system,this paper analyzes the influence of clock jitter on the ultra-high-speed data acquisition system and the uncertainty of asynchronous reset between multiple ADC in detail.3?The research and design of the transmission scheme of high speed data receiving and processing in the multi clock domain.The clock scheme of high-speed data receiving and processing in FPGAs are analyzing in depth.A high-speed data reduction module based on ISERDES,hardware uniform pumping module,a high-speed data cache module based on FIFO,source synchronization data transmission module between multilevel FPGA,the synchronization of multi ADC data cross clock domain,the waveform matching module of 20 GSPS.4?Aiming at the problem of data synchronization between multi ADCs and multi FPGAs based on parallel architecture,a multi-channel data synchronization model in TIADC system is constructed.The data mismatch caused by the uncertainty of synchronization and its root are analyzing.By summarizing and comparing the synchronization schemes between multiple ADC and multiple FPGA,a synchronous reset system based on parallel architecture is designed.A fast and convenient auto-correction synchronous method based on the test mode of ADC is proposed,including an automatic calibration method of BUFR synchronous reset between multi cores of single ADC,an automatic correction method of synchronous reset of single ADC,an automatic correction method of synchronous reset for multiple ADC and an automatic correction method for real-time storage synchronization with multiple FPGA.Through the debugging of each functional module and the test of the performance of the whole system,the design of dual channel 20 GSPS digital oscilloscope data acquisition system,such as sampling rate,resolution,inter channel synchronization delay and other main indicators,has met the design requirements.The sampling rate,resolution,synchronization delay between channels and other main indicators of this data acquisition system of the dual channel 20 GSPS digital oscilloscope meet the design requirements.The fast and convenient method for synchronous self-correcting of multiple ADC and multiple FPGA ensures the stability and reliability of the TIADC system.