Design Of Synchronous Trigger Delay System For Sampling Oscilloscope

Sampling oscilloscope is a high-bandwidth optical/electrical communication signal acqui sition and analysis device based on the principle of equivalent time sampling.Equivalent time sampling means that periodic and digital signals are collected and reconstructed in different c ycles.Compared with real-time sampling oscilloscopes,equivalent time sampling can realize high-bandwidth acquisition of high-rate signals at a lower sampling rate.In order to accuratel y reconstruct the signal under test,it is necessary to precisely control the sampling points of th e sampling oscilloscope in different signal clock cycles,that is,to generate an incremental del ay trigger sequence synchronized with the signal under test.To this end,this paper proposes a synchronous trigger delay generation module of "FPGA+PLL+cascaded delay line" to generat e synchronous trigger delay sequence to drive the high-bandwidth sampler to work and realize the equivalent time sampling of the measured signal.The research contents of this article are mainly elaborated from the following aspects:Firstly,The equivalent sampling method and principle are studied,and various delay met hods are analyzed for the synchronous delay function used to drive the high-bandwidth sampl er.A multi-level delay based on "FPGA + PLL + programmable delay chip" is proposed meth od and theoretical analysis.Secondly,Developed a hardware circuit with the structure of "FPGA + PLL + programm able delay chip ",selected high-speed devices for circuit design,completed the Coarse delay c ircuit,fine delay circuit,signal conditioning circuit,differential The hardware circuit is realize d by amplifying circuit,FPGA circuit,channel selection circuit and power supply circuit.Thirdly,The FPGA is used as the main control chip to design the software of the synchro nous trigger delay system.The frequency measurement of the external trigger signal is compl eted by equal-accuracy frequency measurement,and then the PLL parameters are calculated a nd the PLL configuration is completed.After the FPGA counts the synchronization signal out put by the PLL,a 50 KHz synchronization pulse signal is generated.The signal enters the coar se delay realization program to realize the coarse delay by counting the PLL output signal,an d then configures the delay chip to realize the fine delay,resulting in a maximum delay accura cy of 5ps.,Step delay pulse output with delay range of 1us.Finally,For the developed synchronous trigger delay system,the function verification an d performance test are carried out to realize the generation of high-precision step delay pulses.The delay resolution is 5ps and the dynamic range can reach 1us.According to the equivalent sampling principle,the maximum can achieve 200 GSa/s Equivalent sampling.