Design Of The Digital S Mode Reply Module Of Integrated Anti-collision System

With the increase of the demand for air traffic,civil aviation anti-collision system has also experienced several stages of development.From the beginning of program control as the core of the Air Traffic Control,to the automation as the core of the Traffic alert and Collision Avoidance System,is now proposing the TCAS Ⅱand S mode transponder integrated system.Considering the cost and compatibility of the equipment,how to better integrate the traditional TCAS and S mode transponders is an urgent problem to be solved.A feasible integration scheme is described in this paper,the scheme includes three aspects:antenna integrated,signal processing integrated,and core processing unit integrated.On this basis,the design idea of s-mode response module of integrated anti-collision system is put forward,and its implementation and verification are carried out.According to the comprehensive design scheme,S mode transponder need to exchange information with TCAS system,so the S mode transponder should be able to receive query signals from different communication modes.And each mode should have a decoder.After S mode transponder receives a RF interrogation signal,the signal will be mixed,and then changes to a medium frequency.For processing medium frequency,this paper uses a scheme of the medium frequency digital.The scheme like this,first is the medium frequency A/D sampling,and next is digital frequency conversion,then the data rate of signal can be handled by a FPGA chip,last is decode signal and get information from it.S mode inquiry head is PAM modulation,and the message is DPSK modulation.So this design takes two plans,orthogonal coherent demodulation and DPSK differential coherent demodulation,to obtain demodulation signal.When the baseband modulation signal has got from the scheme,next step is pattern matching.The specific method is to extract PSV signals,and design matching window function reference to the standard.The function will output mode symbol information when the match successful,and gives up the data when the match fails.After the completion of the technical scheme design and demonstration,based on the advantages of FPGA,this paper chooses the hardware description language VHDL to realize the module.First,selecting an appropriate FPGA chip according to the performance requirements of the system.Then use some design principles to decompose the system into multiple sub-modules,determining the interface information of each module,drawing the internal flow chart of the signal processing module,and implementing each module with source code.After that,the simulation signal generated by MATLAB is used to simulate the response module.Through the analysis of simulation results,it is found that the design has too long processing time for A/C mode inquiry signal,resulting in the failure to respond in the specified time.Finally,the design module is tested on board.Using the USB port to grab the real time signal,compared with the expected in the Altera SignalTap Ⅱ logic analyzer,it was found that the module correctly detected the inquiry signal.