Design And Verification Of L2Cache Based On Multi Bus Reconfigurable Processor

The rapid of the processor and memory access faster by the development of the integrated circuit, memory speed although also in growth, but is far less than the processor access speed. It is due to the speed of the processor and memory access has a larger gap. And the problem is more and more serious, so in order to effectively solve this problem, modern design use multistage high-speed buffer memory to balance the difference between the processor and the memory access, solve the imbalance problem, so the design of the second level caches also was born. It has become increasingly important, has become a key factor that influences the performance of the computer.This paper is mainly designed for L2 Cache, it is placed between the processor and the PLB arbiter, which can effectively save the access bandwidth of PLB. The L2 controller is through the DCR bus to complete the operation of the read and write and reset of the register, and configurate the L2 Cache parameters of each module. Through the SRAM interface to realize data storage control function. When all the modules at the same time to access the L2 Cache, it defines a priority and send a priority request. The main use of Tag parity method, according to the Tag bit to determine access to the location, and check whether the shooting. Using LRU algorithm as the substitution method. When a write operation, if the write operation processor hit L2 Cache, the data will be cached to L2 Cache, if no cache hit is not. In the read operation, when L2 Cache hit the PLB request will terminate within a cycle in the PLB device after the effective arbitration. When L2 Cache misses will choosing a Cache pathway to the processor returns a Cache request in the basis of LRU algorithm and the invalid data bit, and writes the data in L2 Cache.The design needs to be verified, verification method which is used in functional verification method. The module level verification is carried out under the Windows system using the questasim simulation tool, and system level verification using NC-sim simulation tool to verify in the LINUX system. The results can be viewed through the waveform or Log file. The completion of the L2 Cache register verification and functional verification, finally realizes the high hit rate of the four groups connected to the cache function. The L2 Cache design and verification, we solve the problem of the speed difference between processor and memory access, to the important role of the entire project completed, the system will be more perfect.