Design And Implement Of The Sine Interpolation Algorithm Based On A Reconfigurable SoC Platform

The sine interpolation algorithm is a method to reconstruct the original signals from a sequence of discrete data in digital signal processing or image processing.The algorithm can be widely applied to restore the discrete signal or reconstruct radar image.Reconfigurable processor is a hot spot of processor research over the recent years.The specific processor architecture has the ability to make substantial changes to the data path itself in addition to the control flow according to the configuration and requirements.In this way,reconfigurable processor combines the flexibility of software with the high performance of hardware.In this thesis,we designed and realized the 1D and 2D sine interpolation algorithm,and implemented it into a chip with high performance based on a kind of Reconfigurable application specific processor.RASP is capable of reconfiguring the topology and interconnection of reconfigurable processing units in the manner of coarse-grained static configuration and accelerating computing in the way of resource reusability.In condition of the algorithmic feature and resource of RASP,we designed a high-precision sine interpolation unit with low hardware complexity and achieved maximum performance.According to the throughput requirement of the sine interpolation algorithm,we designed a specific data access module with data fetching unit and calculate preprocessing module as well as the corresponding control unit.According to the limit of on-chip memory resource,we designed the ping-pong compute mode for small matrix and specific big matrix mode.Hence the design can process matrix in a large scale and perform well at the meantime.According to the poor performance of the divider IP in RASP,we designed a specific module using the technique of reduction of fractions to a common denominator and replace the divider by mac unit.Finally,we finished the verification of design with Universal Verification Methodology and FPGA.We presented the coverage report and accuracy report with the corresponding analysis.Synthesis results show that the sinc interpolation unit can work at 1 GHz and the area is 392820?m2 at 40nm technology.The processor meets the demand of high-speed signal processing.