Design And Implementation Of The Dual-mode Single-chip UHF RFID Reader Digital Baseband Receiving Link

In recent years,with the rapid development of the Internet of things industry,Radio Frequency Identification technology(RFID)has got more and more attentions,and has been widely applied and developed.Currently,in the UHF band,the ISO18000-6C is considered as the international mainstream standard protocols.In order to adapt to the development of RFID and accelerate the construction of the Internet of Things,china has also began to the study of the agreement and implement the UHF RFID national standard GB / T29768-2013 in 2014.Therefore,this project is intended to research a UHF RFID reader that not only supports ISO 18000-6C international standard protocols,but also support the national standard GB/T29768-2013,which can meet the needs of both the international market and local products,what’s more,the applicability of which has great market development and significance.This paper is a sub-project of that project,design and implementation of the dual-mode single-chip UHF RFID reader digital baseband receiving link.First of all,this paper analyzes and compares ISO18000-6C and GB/T29768-2013 in detail,including the transmission link,the receiving link,the communication instruction and the anti-collision mechanism,even discussing the receiving link in detail.On the basis of this protocol,the whole digital baseband is systematically analyzed,with analyzing the digital baseband receiving link in detail,and conduct the design of the index and the design of the whole digital baseband receiving link.Then,based on the modular design as the main method,the digital baseband receiving link and the control unit module that related to the receiving link are analyzed and designed,and realize through verilog and simulate the function.The digital baseband receiving link module includes a symbol synchronization module,a decoding module and a CRC check module.The control unit module that related to the reader digital baseband receiving link includes a protocol control signal processing unit,an interface module and a receive FIFO unit.The symbol synchronization module is the focus and difficulty of the whole digital baseband receiving link,with adopting a novel and improved edge zero-crossing detection structure,which it can correctly synchronize and judge under the 10 dB SNR digital baseband signal.The performance of the structure meets the requirements,with less area resource consumption,easy to achieve,the advantages of fast synchronization.Finally,we actually verify our design of the digital baseband receiver link bybuilding the FPGA test platform which using Altera Corporation Stratix III series EP3SL150F1152C2 to joint to the reader RF analog module to build a complete set of reader system.Besides,the digital baseband receiving link that through the verification is implemented on the SMIC 0.13 μm process.The size of the reader digital baseband receiving link layout is 280228 μm2.The simulation results of the layout parasitic parameters meet the design requirements.