Optimization Of AES Algorithm Hardware Implementation Based On FPGA And Design Of Its System

Users need to encrypt the data to ensure that their important information or data is not stolen by third parties which is unauthorized in the network and communication.Usually,the most popular form of data encryption is software encryption that is implemented with programs on a general-purpose microprocessor.But its encryption speed is generally not high,its algorithm implementation is low efficient and its security and reliability are limited.It can’t meet user needs in many cases.Therefore,a faster,more secure and reliable implementation of cryptography is needed to satisfy data security requirements in some occasions.Encryption algorithm based on FPGA has advantages of high security,fast encryption speed,short development cycle,low cost,reconfiguration,high reliability,good portability and so on.This kind of data encryption has gained more and more attention in the network and communications.On the basis of studying basic principle of AES algorithm and its related mathematical theory,a FPGA-based hardware implementation of AES algorithm is optimized from four aspects.Firstly,we use mixed pipelined structure in the overall design: fully expanded pipelined structure is used between round iteration,and the pipelined structure is used in each round.Secondly,substitution bytes and shift rows are integrated implemented to reduce resource occupation of shift rows;substitution bytes module,MixColumns module and key expansion module are optimized by lookup table to reduce computational complexity and resource occupation;by finding the critical path and optimizing the path,the encryption speed is increased again.Thirdly,encryption process and decryption process share the key expansion module and lookup table module to reduce the consumption of programmable logic resources.Finally,FPGA-embedded RAMs are used to store lookup table in order to further reduce consumption of FPGA chip area.The optimized AES algorithm is used to synthesize,timing constraints,place and route on the FPGA chip.At the same time,the parameters such as resource consumption and operating frequency are obtained,and compared with similar researches.The results show that our design achieves faster encryption/decryption rate and lower resource occupation;it has a greater advantage in the encryption/decryption efficiency.The optimized AES algorithm is packaged into an IP soft core by using custom IP core technology,and the IP core is easy to be multiplexed on any FPGA chip.Finally,the AES encryption/decryption system is designed based on the custom AES IP soft core.The AES encryption/decryption system is simulated and validated on the professional simulation tool Modelsim,and then Quartus II integrated development environment is used to synthesis,place and route,timing constraint.Finally,the AES encryption/decryption system is downloaded to a DE2 development board for verification.The result shows that it can run normally at a clock speed of 200 MHz,and the encryption speed can reach 6.4Gbit/s,which can satisfy the data encryption in most networks or communication.The whole system has the advantages of simple structure,free configuration function module,high security,good portability,easy maintenance in real time,and can be widely used in various information security fields.