Research And Realize Of One Wideband Full Digital Radar Receiver

This paper tightly focus on RF full digital radar receiver design.In order to receive and deal with L-band radar echo from horizontal and vertical polarization channel,we have studied receiver interference suppression ability,signal effectively receive,and how to enhance the recevier’s capability to form a fine afterward wideband echo imaging.Therefore,the study paper mainly talks about the following aspects:In chapter two,we study the interference suppression in radar receiver filters and key performance of front-end gain amplification.Then ADC device selection is performed from dynamic range,ADC noise deterioration and board design model.In the third chapter,we study the clock quality of receiver,problem of channel mismatch and technology of echo receiving and processing.An algorithm of L-band clock jitter estimation and separation is presented.A method of amplitude and phase error estimation in time domain and correction in frequency domain is proposed.According to the chip features that digital down converter is built in AD9680,resign and application of AD internal DDC in direct sampling platform is researched.The implementation process of high-speed serial protocol JESD204 B between AD9680 and FPGA is researched.The fourth chapter talks about system implementation and results analyze.In this paragraph,we study FPGA data capture process.What’s more,clock jitter algorithm simulations is researched.MATLAB results show that for simulation signals,the algorithm can calculate the true size of the jitter and separating it from the signal;for measured signals,it can calculate the approximate value of the jitter.Channel mismatch correction method in study of measured data is present.It also includes the dynamic performance of the ADC and DDC performance,the process of environmental clutter simulation and echo signals acception in actual target field observation.