Scheduling Technology For Image Processing Operator On Reconfigurable Processor

Compared with general purpose processors and application specific integrated circuits,reconfigurable processors are better for executing multimedia application benefiting from the trade-off of efficiency and flexibility.A reconfigurable processor is composed of a general purpose processor and a reconfigurable computing array,where the general purpose processor is used for some control tasks and the reconfigurable computing array can flexibly change operations according to the configuration information to realize parallel computation.In order to realize support for video mosaic library on reconfigurable processor and research parallel compiler,the high-efficiency scheduling method is studied in this paper.Firstly,the registration accuracy,matching robustness and other issues are deeply analyzed based on our research for traditional image mosaic methods.An improved image feature point detection and mosaic method is proposed.Its performance and robustness are analyzed compared with other four classical methods.Then we analyze the data dependency of each computational node in loops from the source code.According to the functional characteristics of operators on reconfigurable processor,loops are splitted into the set of operators with loop optimization technique.And those operators are reordered with parallel-pipeline scheduling technique under the condition of increasing temporal locality and spatial locality of data.At last,the mapping from instructions of general architecture to operators of reconfigurable architecture is realized.Compared with programs on general purpose processor,the key scheduling technology for image mosaic algorithm on reconfigurable processor is tested from two aspects of function and performance.In order to verify the functional correctness of parallel split and mapping,the mosaic results of reconfigurable processor are compared with that from our image mosaic and evaluating software system which also can realize time complexity analysis of algorithms.The efficiency of parallel configuration information on reconfigurable processor and serial C code on Atom 230 processor is respectively tested with the Embedded Microprocessor Benchmarks by repeating 100 times.The results show that speedups of Harris algorithm,normalized cross correlation algorithm,random sample consensus algorithm and Gaussian Laplacian edge detecting algorithm respectively achieve 3.75,2.68,11.27 and 12.27.The execution efficiency of these image processing methods is improved largely.