Research On Test Data Compression Method Of Optimizing Shift-and Capture-power Simultaneously

With feature size shrinking and integration level increasing,the number of transistor and the complexity of function increase drastically,which is a severe challenge to the VLSI test.Large test data volume and high test power are among the main problems of VLSI test and they have a severe effect on test cost.Thus,Research on high-compression-ratio and low-power test method is of great importance.Aimed at this problem,this thesis makes research on reducing both shift power and capture power while enhancing compression ratio simultaneously.The main work is as follows:The proposed low-power multistage test data compression scheme first preprocesses the original test set with the input reduction technology so as to reduce the volume of specified bits;secondly,the scheme compresses test patterns shifted in multi-scan chains according to their compatibilities and uses shorter code to demonstrate compatible test patterns,namely the first stage of compression;thirdly,the low power X-filling is conducted: X-filling for capture power reduction is first conducted for the unspecified bits to keep the capture power under the given threshold and then the remaining unspecified bits are filled for shift power reduction;finally,the proposed scheme further compresses test patterns using modified run-length coding.Experimental results for ISCAS89 benchmark circuits demonstrate that,compared with golomb,FDR,EFDR,9C,BM code,etc.,the proposed scheme achieves better compression rate while reducing both the capture power and the shift power.The proposed tri-state-controlled low-power LFSR reseeding classifies scan slices into three types and utilizes tri-state signal to encode each type of scan slice to reduce the volume of specified bits in test set.Tri-state signal are utilized as the flags of scan slice and there are lots of serial sequence which can be compressed.A low-power decompression structure is proposed last to decompress low-shift-power test pattern.The decompression structure can avoid capturing test response of part scan chains which are irrelevant to the observing fault.Experiment shows that the proposed method can effectively reduce shift-power and capture-power without compression ratio loss while increase the compression ratio.