Research And Implementation Of RO Based Addressable Test Chips

With the critical dimension shrinking to the physical limit gradually,the design rule and manufacture process of IC have become more complicated,which has also induced a worse decrease in yield.The test chip,which integrates the test structures of electronic and physical parameter extraction,and process defect monitoring,is playing an especially important part in the field of IC yield.As a kind of test structure,RO(Ring Oscillator)is often utilized for delay measurement,AC parameter extraction and process variation monitoring.In order to increase the density of test structures integrated in a test chip,addressable method is brought up and widely used nowadays.With the density increased for test structures,it has been more troublesome for the layout generation,even worse for complicated structures such as RO.If we apply software and layout database for layout automatic generation,as are used in EDA(Electronic Design Automation),the time spent on layout generation will be saved and lots of manual errors may be avoided.This article focuses on the research of RO-based test chips,and a complete solution is promoted:An area efficient addressable test chip design based on RO,which can be placed in scribe lines for WAT,with a dedicated layout automatic generation platform to save design time.This method also takes care of the details for test accuracy and convenience as follows:(1)Considering the variety of RO types and output frequencies as the addressable method is introduced,a 2-level frequency divider which is composed of a local and global divider,is utilized to reduce all RO output frequencies to a narrow range so that they can be measured accurately by testing equipment;(2)Considering the accuracy of the current measurement,2 sets of separate power/ground nets are used for RO and peripheral circuits respectively;(3)Considering the accuracy of the supply voltage,a new addressing method combining "one-hot" code with traditional binary coding and decoding is put up,and "mesh routing" method is used to further reduce the IR drop on power and ground nets.This scheme has been implemented at 16nm FinFET,28nm CMOS and many other advanced process nodes from international mainstream foundries,with simulation and testing data as proof for its feasibility and reliability.