The Design Of High-Speed FIR Filter Based On Distributed Arithmetic And Implementation By Using FPGA

The phase shift of FIR filter has linear characteristics,and it is an important unit in the field of digital signal processing.With the rapid progress of information technology,real-time signal processing has become an urgent demand for modern electronic systems.Based on the multiply-accumulate FIR filter,the operating speed cannot meet the real-time signal processing requirements.Distribute arithmetic that is a new approach for the implementation of high-speed FIR filters realizes complex multiplication by lookup table operation,and then combines simple addition operation to complete the real-time filtering operation.This article studies the design and implementation of high-speed FIR filter based on distributed arithmetic,and uses FPGA as the realization platform of high-speed FIR filter.Firstly,the research background,application significance and the latest research methods of high-speed FIR filter are discussed.Then the influence of structure and design method on filter performance is analyzed.And then it focuses on the design of distributed architecture FIR filters.On the basis of traditional distributed architecture,three kinds of improved distributed architecture are proposed,namely,the partitioned lookup table serial distributed architecture,the partitioned lookup table parallel distributed architecture,and the partitioned lookup table string and combined distributed architecture.The lookup table partition optimization method and the pipeline structure adder design provide the theoretical basis for high-speed FIR filter implementation.Secondly,the coefficient design and quantization width of the high-speed FIR filter are studied.The optimal quantization width of the coefficient is 12 bits,which is determined by visually comparing the approximation error.Afterwards,taking the partitioned lookup table parallel distributed architecture as an example,the distribute arithmetic idea is converted to the hardware unit design,and a functional simulation and a timing simulation are performed.From the timing report,the maximum operating frequency of the 64-tap FIR filter is 406.174 MHz.Finally,the performance test on the ML509 board with the core of the XC5VLX110 T chip is performed.And compare the test results with the theoretical value of Matlab,the deviation error is small.By comparing the input and output waveforms collected by the ChipScope tool,the designed high-speed FIR filter has the performance of real-time filtering.The data analysis of the test results based on three distributed structures validates the superiority of the parallel distributed architecture design of the partitioned lookup table.Eventually,the deviation factor between the test result and the theoretical value is analyzed,and the performance of the high-speed FIR filter is verified from the frequency domain.