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High-speed Fir Digital Filters Implemented On Fpga

Posted on:2009-08-04Degree:MasterType:Thesis
Country:ChinaCandidate:B P LengFull Text:PDF
GTID:2208360245460850Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Generally the device used for real time DSP includes programmable DSP chipset(such as TI,AD),ASIC and FPGA, etc. In engineering practice, there is always a high-speed,real-time and flexible requirement for signal processing. However, software and hardware techniques available for implementation are difficult to meet the demand for the several aspects in the same time. Along with the development of PLD device and EDA technology, FPGA not only meets the real-time requirement, but also has some flexibility to implement DSP. In recent years, FPGA has the characteristics: flexible programmable logic which can be conveniently used to implement high-speed digital signal processing, for it break through the level limit of parallel and pipeline, reconfigurable logic resource on chip thus the resource can be utilized effectively. More and more researchers who engage digital signal processing are favoring FPGA.The FIR digital filter is used for many practical applications for its good linear phase character, and it provide an important function in Digital signal Proeessing design. In this Paper, a method to implement the FIR filter using FPGA is proposed. The work mainly includes:1. The basic theory of FIR digital filter is introduced and the development situation, the design flow, the design principle, the commonly used design method and the technical of FPGA are discussed.2. According to the basic theory of FIR filter, a scheme of hardware implementation is worked out using distributed arithmetic algorithm. As the scale of the LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks that use the optimized distributed arithmetic algorithm.3. Implement a 192-order FIR filter example. its demands: 16 bits fixed input-data, 12 bits fixed coefficient, 16 bits fixed output-data, and 75MHz. The designs are simulated by Quartus II software. And compare Quartus II simulated result with Matlab simulated result. The result of the simulation indicates that the scale of the design is small, and the sample rate of the FIR filter can reach 75MHz. Modifying the LUT can realize the low-pass, high-pass and band-pass FIR filters respectively, and incarnates the flexibility of the design.
Keywords/Search Tags:FIR Filter, Hardware Description Language, Distributed Arithmetic, Look UP Table, FPGA
PDF Full Text Request
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