Research And FPGA Implementation Of Physical Downlink In LTE-A System

In order to meet the currently growing demand of mobile communication system capacity and transmission reliability,orthogonal frequency division multiplexing technology and enhanced MIMO technology are being used in the Long Term Evolution-Advanced system.With the large-scale introduction and construction of LTE-A networks,the substantial increase of system capacity and data transmission rate brings more challenges for LTE-A system test equipment and software.The fact that whether the receiver can accurately recover and analyze the signal will determine the performance of the whole system.The process and implementation of physical downlink are the key parts of the whole LTE-A system,and these are also the difficult parts of the present research.A powerful parallel processing capability and rich resources of the Field Programmable Gate Array(FPGA)can provide an excellent baseband platform for LTE-A system.Based on the background of "LTE-A downlink signal processing FPGA and DSP software" project and combined with the project requirements and LTE-A protocol standards,this thesis,targeted to optimize the system performance and meet real-time requirements,focuses on the research and implementation of the LTE-A physical downlink receiver,and gives the corresponding FPGA design method.The main works are as follows:1.The performance and complexity of different channel estimation algorithms and interpolation algorithms are compared and analyzed.The LS algorithm and the first order linear interpolation are used as the FPGA implementation scheme.In the 20 M bandwidth,the consumption time is about 0.84 ms verified by baseband platform,can satisfy the project requirement.2.Research and performance comparison of different signal detection algorithms for downlink are carried out in the thesis.In order to overcome the shortcomings of sphere decoding,a greedy strategy sphere decoding(SDBGS-M)algorithm based on M algorithm is proposed,it makes the radius converge faster,which can commendably reduce the complexity.The detection complexity of SDBGS-1 is reduced by about 22% compared with traditional SD algorithm.For 8 antennas QPSK system,it can be reduced by 25%.3.Considering the requirements of the project,the whole system is under the transmission diversity mode.The thesis mainly uses the Space Frequency Block Code algorithm,and gives a detailed FPGA design method.In the 20 M bandwidth,the consumption time of single OFDM symbol is about 0.008 ms verified by baseband platform.Meanwhile,based on this,the QR decomposition detection algorithm is implemented on FPGA.4.The process of downlink channel resource mapping and the main processing module of the downlink channel are analyzed and detailed designed on the FPGA.And the simulation and verification of it are completed on the baseband platform.Finally,the overall simulations of the channel estimation,signal detection,resource demapping,PBCH,PCFICH,and PDSCH receiver are completed.Time series analysis and resource usage analysis are conducted,At the same time,the implementation of scheme will also be applied to the actual development of the project.