Hardware Implementation Of μC/OS-II Communication Mechanism Based On FPGA

Nowadays the operating system is independent software system,such as Windows,Android,iOS,embedded systems such as Vx Works,ect.The PC is completely divided into two parts: the software part and the hardware part.This partitioning mechanism has already made great progress in technology.However,with the continuous development of chip technology and Internet of Things technology,this partitioning mechanism fails to meet the demand of current society for the operating system in all aspects,we need technical innovation.The hardware of the operating system becomes a new technology to solve the problem of partitioning between hardware and software.The hardware of operating system has two methods,one is hardware of whole OS,another is hardware of the part of OS.Due to the hardware of whole OS is low of using scope,changing too fast,technology too complex,we often use the hardware of part of OS.It means that a real-time OS is divided into H/W and S/W,some time-consuming task are changing to implement through hardware.Reasonable division of hardware and software will be able to enhance system performance and reduce the running time and task response time.This thesis is based on the RTOS μC/OS-Ⅱ,we implement the mutex semaphore and message mailbox of μC/OS-Ⅱ through the hardware.Using the Verilog HDL implement creat、post、pend、delete function in the task communication mechanism.Real-time operating system’s S/W only need to send the task command word to the hardware logic,then the hardware implement these functions.ALTERA company’s DE1-SOC development board has built-in CYCLONE V FPGA and ARM A9 processor,it’s function is very powerful.This design will ultimately achieve that the H/W will be deployed to the FPGA area of DE1-SOC.And,the S/W will be translated to the CORTEX-A9 to built a completed HERTOS.