| At present,the IC industry has developed rapidly,and the IP nuclear research and development of the chip has been paid more and more attention.At the same time,the design of the open source instruction set architecture chip has become the mainstream.So the research and development based on the RISC-V instruction set CPU has become the main direction of the development of the major traditional IC companies and institutions of higher learning.The most important part of the processor is the operation module,so the computing power of the RISC-V processor is particularly important.This paper focuses on the design of the operation module.The design of operation module in this paper is designed and implemented according to the method of partial local assembly.First,each functional module of the operation module is designed one by one,and the final assembly is simulated and transplanted to the open source RISC-V instruction set architecture IP core for entity verification.This paper uses the pipelined structure used by the processor.The operation module of this paper uses the RISC-V instruction set to design the bucket shifter in the combinational logic unit,the adder and multiplier in the arithmetic logic unit.Barrel shifter uses two schemes: full decode and partial decoding,and selects the faster full decoding mode.In the arithmetic logic unit,we adopt the optimization method of resource sharing,transform all the logical formulas in the unit,and design the arithmetic logic unit based on resource sharing.The multiplier uses an improved base 4 Booth algorithm to optimize the partial product,and by mathematical calculation preprocessing symbol extension,the partial product symbol extension circuit is simple and regular.The Wallace counter is realized by using 4-2 counter to accumulate part time and improve the speed and performance of multiplier.In a clock cycle 87.779 s,12376238 instructions per second are executed on a saturated frequency of 12.376 MHz. |
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