Pipelined CPU Design And Verification Based On MRK?e Instruction Set

MRK? instruction set and its extension MRK?e instruction set is a non-open source RISC designed by NXP,which is widely used in on-board intelligent electronic devices.The research,design and verification of CPUs based on MRK? instruction set and its extended MRK?e instruction set are helpful for the development of autonomous vehicle CPU instruction sets.Based on the research and analysis of MRK? and its extended MRK?e instruction set,a CPU core that conforms to MRK? instruction set is designed by using a two-level pipelining structure,which supports instruction prefetching mechanism to ensure the fast fetching process under the tight instruction storage.The CPU core can support user and system two modes,so that the key data and other information are protected.On the basis of MRK? CPU core,the structure extension is carried out to realize the MRK? extension instruction.The new structure includes bit operation mask generation unit,multiplier,divider and other units.The bit operation mask generation unit converts the source operand into the mask operand through inversion,shift and other operations,and then carries out logical operation or move operation with the destination operand.Based on the distributive law of multiplication,the multiplier element decompositions the long multiplication into the short multiplication to reduce the area.Based on subtraction operation and shift operation,the divider decomposes the operation into multiple cycles to reduce the consumption of hardware resources.The simulation results show that the designed CPU core correctly executes all the instructions and various instruction combinations of the MRK?e instruction set.A minimum system based on the designed CPU core is implemented by Zynq7020.The logical synthesis results show that 6598 LUTs(lookup tables)and 714 FFs(triggers)are occupied by the CPU core,of which only 70 LUTs are occupied by the multiplier and 456 LUTs are occupied by the divider.Under the condition of CPU frequency of 16 MHz,the running program of the minimum system is correct and meets the design requirements.This design can provide some reference for the design of automotive CPU core of autonomous instruction set in the future.