Research On Acceleration Technology For Fdtd Based On Vivado HLS

In the field of computational electromagnetics,finite difference time domain method(FDTD)has been widely used.Using FDTD,the electromagnetic distribution of the whole field is obtained by alternating calculation of the electric and magnetic field.For many electromagnetical computational problems,FDTD is the simplest method,in consideration of conception and achievability.Although FDTD can solve complex electromagnetic computational problems,it consumes substantial computer resources and plenty of time.To obtain fast and efficient results,hardware acceleration needs to be used.In recent years,researchers concern about combining hardware acceleration with FDTD in the research area of computational electromagnetics.Various methods have been proposed to improve the computing speed of FDTD.Recently Xilinx introduced a new advanced synthesis tool,Vivado High Level Synthesis(HLS),which develops hardware system through C/C++ Systems.Tools in HLS automatically generate timing according to the algorithms,which is much more simple and efficient compared to traditional hardware design.To accelerate the calculation of FDTD algorithm,in this paper we analyze the computing bottleneck of FDTD based on some of the principle of it.We use HLS tools to optimize the design of one and two dimensional(1D/2D)FDTD,and verify the effectiveness and advantages of the method through a few examples.The main works of this paper are described as following:First,we analyze the basic principle of FDTD algorithms and deduce the iterative formulas of the 1D/2D FDTD.We study the absorption boundary conditions(ABCs),and emphatically introduce the perfect matching layer(PML BCs).The numerical stability of the FDTD algorithm is discussed.Besides,the optimization strategies for synthesis are studied.Secondly,we propose a pipelined FDTD algorithm architecture to realize the calculation of the electric and magnetic field.We discuss 1D/2D FDTD algorithm with C model.Based on the FDTD architecture,HLS tools are used to conduct the analysis.By scheduling and binding,we optimize the algorithm as follows:adding array partition constraints to improve data access speed,adding unroll constraints into the loop to shorten the latency,adding pipeline constraints into the loop to establish a pipeline structure.Besides,the RTL function simulation is carried out through testbenching and imaging the date result by using MATLAB.Finally,we optimize the 1D/2D FDTD examples to validate the correctness and efficiency of the proposed optimization programs.Our final results show that the method has a high data throughput and fully uses the parallel and pipeline computing advantages of FPGA.Besides,the design method has the characters of low complexity and low cost.Both aspects show practical applications in the hardware acceleration of the finite difference time domain method.