Research On ESD Protection Design And Characteristics Of Integrated Circuits Under Advanced Process

ESD is a fairly common concept that occurs in almost every place.In the semiconductor industry,as semiconductor processes become more advanced,devices become smaller and more complex,the potential destructiveness of ESD in integrated circuits(ICs)becomes more serious,so ESD protection research is very important.This paper performs a complete ESD test and failure analysis on the specific application chip,analyzes its failure mechanism and the weak point of the chip ESD and proposes ESD protection improvement based on the currently advanced 28nm CMOS and GaAs PHEMT process.Novel devices that conform to the ESD protection window are designed under the corresponding process.Finally,ESD characteristics and resistance defects are studied under different ESD protection structures,including diode,GGNMOS and RC trigger NMOS.The main contents and innovations are as follows:(1)Protection design difficulties and requirements under advanced 28nm CMOS technology are summarized.The ESD design window under typical 28nm CMOS technology is given.Two typical ESD protection networks in nano-integrated circuits are proposed,and their advantages and disadvantages are summarized.(2)A comprehensive ESD test and failure analysis of a 28nm CMOS process chip in a project has been carried out.It is found that the weak point of the ESD protection of the chip is that the on-resistance of the ESD Clamp device is too large,causing the voltage of the clamp to be too high to damage the PMOS/NMOS output tube and internal core circuit.Through the comprehensive failure analysis of the chip,the failure mechanism is summarized and the optimization suggestions are put forward.(3)A novel double snapback MOS-SCR device is proposed and typed out in 281nm CMOS process.The structure embeds a GGNMOS structure in a conventional SCR thyristor to enable the GGNMOS and the SCR to conduct,SD current together,Through TCAD simulation,the ESD test of device and some failure analysis verify the working mechanism of the MOS-SCR.By adjusting the device parameters,MOS-SCR devices can have low trigger voltage,high holding voltage and high robustness.MOS-SCR devices are well suited for ESD protection in 28 nm CMOS processes.(4)The function and application of the high-speed optical module power amplifier chip of GaAs process are introduced.The TCAD simulation of the core device PHEMT under GaAs process is carried out,and its working principle is analyzed.The characteristics of the device under DC and transient ESD conditions are simulated,which helps to better carry out ESD protection design of related circuits.The ESD robustness test and ESD failure analysis of a specific GaAs PHEMT high-speed optical module power amplifier under TLP and HBM test systems were carried out to detennine the ESD failure mechanism and weak points of the GaAs process.(5)The Schottky diode string structure formed by GaAs PHEMT device is proposed,and the chip is verified under the relevant process.The trigger voltage is 0.7V.According to the specific ESD protection window of the VC chip of the optical module chip,the ESD protection of the Schottky diode string is added to the pin to increase the HBM rating from 350V to 750V.A novel ESD protection device using diode-triggered PHEMT is also proposed,which has lower leakage current(10-9A)and higher robustness than Schottky diodes.(6)For different ESD protection structures,including the diode' GGNMOS and RC trigger NMOS power clanmp,ESD characteristics and IC resistance defects are studied.The effects of EOS surge waveforms,longer pulse widths and slower ESD pulses on the performance of ESD protection devices are investigated.