| Gallium nitride(GaN)-based blue LEDs(light emitting semiconductors)are widely used in lighting,backlighting,and full-color displays.Due to the large band gap of GaN,the positive and negative electrodes on the same side of the chip and the small spacing,the thin n-GaN active layer,the non-conductive or high resistivity of the Al2O3 substrate,LED chips are often damaged by static electricity during use,resulting in PN junction failure and reduced service life.With the continuous reduction of chip size,its antistatic ability will be weakened correspondingly,and the design of better antistatic chip has become a research hotspot.This thesis improves the antistatic ability of LEDs through chip process design.The design experiment improves the antistatic ability of LED chips from four aspects:chip size,electrode layout design,indium tin oxide(ITO)transparent conductive film parameters and process optimization.The performance,the specific process and the results obtained are as follows:(1)As the chip size becomes larger,the area of the PN junction increases,and the barrier capacitance also increases,which prevents the diffusion of most carriers to each other and improves the chip’s antistatic ability.(2)By increasing the finger of metal electrode,shorten the distance between the P electrode and the N electrode;increase the ability of the current to spread uniformly between the PN electrodes laterally,and increase the ESD(electrostatic discharge)yield of the finger shaped electrode to increase by an average of 29%.At the same time,in order to overcome the problem of charge concentration on the tip,the tip is designed as a circular electrode to disperse the current density.Testing this design will relatively increase the ESD yield by 10%.(3)The ion source coating method has the advantages of high particle energy,good film deposition continuity and good compactness,and deposits ITO films of different thicknesses,from transmittance,LOP(light power)and VF(forward voltage)To compare the difference of different film thicknesses,choose 350A thickness as the optimal parameter.In addition,the ITO aperture under the electrode is reduced from 64μm to 50μm,the current diffusion area is increased by 3.5%,and the test will increase the ESD yield by 5.5%.(4)Choose 300s+100s as the best time to etch ITO to avoid current congestion and leakage caused by ITO over-etching and under-etching.Design ITO shapes with different R angle sizes,and test R25 as the best parameter.The lead time of the photoresist on the CB(current blocking)layer is selected to be within 6 hours,and the slope angle after CB etching will be less than 43° as the best parameter.A small angle can make the ITO film more uniform and continuous.Improve the antistatic performance of the chip. |
