Research On Key Technologies Of Low Parasitic Parameters SiC Hybrid Packaging Integrated Module Based On Stacked DBC

As the core component of power electronics devices,the power module will directly determine the performance of the devices.Compared to traditional Si-based devices,wide bandgap silicon carbide(SiC)and gallium nitride(GaN)semiconductor devices have smaller junction capacitance,faster switching speed,and lower loss,which can significantly increase the switching frequency of the devices.So the power density of power electronic devices can be greatly improved.Therefore,it has been widely used in many fields such as aviation,ship,automotive.However,the high switching speed of SiC devices will generate higher dv/dt and di/dt.Under the influence of internal parasitic parameters of the power module,the device will generate higher voltage stress,oscillation,EMI issue,more switching loss,and shoot-through failure.Therefore,it has become a hotspot research for the popularization and application of silicon carbide devices to reduce the parasitic parameters of SiC power module packaging and obtain clean switching waveforms.In order to reduce the packaging parasitic parameters of the silicon carbide power module,the power device packaging structure can be roughly divided into three categories: wire-bonding structure,planar structure and hybrid packaging structure.Among them,the wire-bonding structure has a simple process and high reliability,but it has large package size is and large parasitic inductance.While the planar structure has small parasitic parameters and good heat dissipation performance,but very complicated entire process and low reliability.And the hybrid packaging structure,which combines the advantages of the wire-bonding structure and the planar structure,has small parasitic parameters,simple process,and high reliability.Therefore,this paper studies the principle and method of reducing parasitic parameters based on hybrid package structure.Stacked DBC is used to optimize the 3D power loop and design a novel high-current silicon carbide power module with very low parasitic inductance.This paper first analyzes the distribution and source of parasitic parameters of the half-bridge circuit.Then,the effect of parasitic parameters on the switching performance was analyzed by electromagnetic field simulation,and the influence of the parasitic parameters on the voltage,current stress,and switching loss of the device was revealed.The results prove that reducing the parasitic parameters can reduce the voltage and current stress and loss of the device.In the third part,this paper proposes a design method to reduce the parasitic inductance of the power loop by using a stacked DBC hybrid package structure,a 3D power loop is formed to achieve mutual inductance cancellation,and the parasitic inductance of the module is significantly reduced.In the fourth part,based on the stacked DBC hybrid packaging structure proposed in this study,a novel low-parasitic 1200V/120 A full SiC power integrated module is designed.The parasitic inductance is only 3.5nH,which is significantly lower than commercial silicon carbide modules.Finally,the static test and double-pulse test of the module are done to verify its low parasitic parameters.The results show that compared with the commercial module,the voltage stress of the designed power module switching process is reduced by 66% and the loss is reduced by 55%.