Design Of Clock Synchronization System Of Linear Superconducting Accelerator

Linear accelerators are one of the first accelerators to appear.Charged particles move along a linear trajectory in a linear accelerator,and are subjected to the action of a high-frequency electric field during motion.The charged particles are accelerated in the high-frequency electric field.Generally,a linear accelerator is composed of a plurality of acceleration cavities,and how to stabilize the frequency,phase,and amplitude of the high-frequency electric field in each acceleration cavity is an important problem to ensure continuous acceleration of the electrons and improve the efficiency of the accelerator.This design provides a clock synchronization system solution for the Institute's 150.4MHz linear superconducting accelerator.The solution includes a high-frequency reference signal unit in a high-frequency system of a linear superconducting accelerator,a 6MHz phase stabilization unit,and a 48-select 1 high-frequency signal switching unit.The traditional high-frequency signal source is generally implemented by a crystal oscillator plus PLL scheme.Although this scheme can meet the clock requirements of high frequency and low phase noise,the frequency and phase of the clock are small and not flexible enough.In order to cope with the research institute's requirements on the frequency and phase adjustability of high-frequency reference signals,the high-frequency reference signal unit in the design uses a temperature-compensated crystal oscillator and a PLL to generate a multiplier clock to the FPGA and DAC,using FPGA to generate DDS data drive DAC to generate high frequency,low phase noise high frequency reference signal.This scheme can meet the low phase noise requirements of high frequency reference signals,and can also meet the requirements of high frequency reference signal frequency and phase adjustment.The 6MHz phase stabilizing unit obtains the reference signal phase and the phase of the signal picked up from the tandem accelerator by the FFT algorithm in the FPGA,and obtains the control signal to the beam pulse by the PID control algorithm.The module,the beam pulsing module outputs a pulse beam to the tandem accelerator,so that the phase of the beam pulse accelerated by the tandem accelerator is stabilized to the high frequency reference signal.48 select 1 high-frequency signal switch unit uses 9 chip 8 to 1 RF switch chip to achieve 64 input select 1 output switching matrix.The 48-select 1 high-frequency signal switching unit outputs the signal fed from the 48-channel superconducting cavity to the control room oscilloscope for observation.The experimental test results show that the function and performance of the clock synchronization system scheme can better meet the requirements of the linear superconducting accelerator clock system.The theoretical analysis and experimental results of this scheme can provide theoretical basis and reference for the subsequent scheme implementation or scheme upgrade.