Research And Implementation Of Power System Harmonic Detection Algorithm Based On FPGA

In recent years,power electronics technology has been developed rapidly,which provides a large number of non-linear loads for the smart grid,generating a plethora of harmonics,reducing power quality and affecting the safe operation of the power system while bringing convenience to people's lives.As a considerable research topic of the harmonic problems,the harmonic detection is of great significance for solving harmonic problems and improving power quality.At present,due to inherent defects of the algorithm,various harmonic detection devices can only detect integer multiple harmonics,and the accuracy of detection is insufficient.On the other hand,due to the nature of the hardware,which leads to the detection of poor real-time performance.In light of this,this thesis studies the theory and implementation of the harmonic detection algorithm and improves the accuracy of the algorithm detection compared with the existing algorithm.With the help of t he hardware acceleration of the Field-Programmable Gate Array(FPGA)platform,the real-time performance of the proposed algorithm is improved evidently.The main research contents of this thesis are organized as follows:Theoretical study of harmonic detection algorithms is presented in the Master's thesis in sufficient detail,and an improved scheme is proposed due to the fact that the Prony algorithm is susceptible to noise.Firstly,the preprocessing algorithm proposed in the thesis is used to preprocess the power signal,filtering the noise component in the power signal and determining the order of the harmonic components.Then,the Prony algorithm is introduced to estimate the frequency parameters of the harmonic components.Finally,the ADALINE neural network is presented to estimate the amplitude and phase parameters of the harmonic components.The simulation results show that the improved scheme proposed in this thesis can greatly reduce the influence of noise signals and has high detection accuracy.Moreover,the realization of the harmonic detection algorithm is specifically analyzed.Aiming at the common issue that the harmonic detection algorithm has high computational complexity and poor real-time performance,the thesis analyzes the numerical calculation process of the algorithm and selects ZYNQ series FPGA development board of Xilinx Company as the operation platform of the harmonic detection algorithm.In addition,the harmonic detection algorithm is implemented by the FPGA.Based on the numerical calculation analysis of the harmonic algorithm,the preprocessing algorithm and the IP core of ADALINE neural network algorithm are designed for hardware acceleration.The ARM processor is used to realize the flow control of the system and the algorithm with less parallelism.The experimental results show that the running time of the harmonic detection device is about 0.262 s,which improves the real-time performance of the algorithm and achieves the expected goal.