Design And Implementation Of ETB Protocol Based On Cyclone V In FPGA

Since the IEC launched the TCN standard in 1999,namely IEC 61375-1,the TCN standard has long been used in train communication networks after nearly 20 developments.Relying on its real-time and reliability characteristics,the TCN standard has been favored by major train network communication equipment manufacturers and supported by many railway operators.The TCN standard network transmission rate limits its further development.and the IEC introduced a new generation of ETB standard in 2011,namely IEC 61375-2-5.This will be a major opportunity for China.At the national strategic level,it is very meaningful to localize its core technology.The "Train reconnection communication technology research and development" project customized based on the "IEC 61375-2-5" standard is to realize the function of network data transmission and ETB network establishment and reconnection.After detailed interpretation and analysis of the ETB standard,a research and development plan based on Cyclone V SoC chip is proposed,and it is divided into HPS part and FPGA part.This paper introduces the hardware and software environment,lists the overall requirements,analyzes the timing control of the MII interface,and analyzes the frame timing function of the TTDP frame.This paper also details the use of Verilog HDL to implement MAC layer MII interface and TTDP frame frame timing function on FPGA,and use HPS bridge to realize data communication between HPS and FPGA.This paper also conducts a comprehensive analysis of the entire project,planning information that needs to be communicated between HPS and FPGA to clarify the specific tasks of the FPGA.First,the requirements of the FPGA are modularized,and a state machine is designed to implement logic control.Then it uses RTL simulation to verify and debug the working status of each state machine,in order to meet the functional requirements,but also have a certain fault-tolerant processing.Finally,on the hardware experiment board,the joint debugging between HPS and FPGA is realized to detect the realization of various requirements of the project.Use SignalTap to capture the actual running waveform to verify the actual operation of the FPGA program.RTL simulation has ensured that the state machine is working properly and fulfills the expected various requirements.In the actual joint debugging,the communication between the HPS and the FPGA is normal,and the jumps of the various state machines of the FPGA are normal,and the operation can be stably performed for a long time,realizing the requirements of the entire project.