Design And Implementation Of FC-AE Bus Fault Simulation Device

With the development of integrated avionics technology,the transmission requirement of large amount information transmission puts forward higher requirements for the speed and bandwidth of interconnected bus.Therefore,fiber channel,characterized by high data bandwidth,high performance communication and long transmission distance is widely used.In the development process of fiber channel equipment,the fault tolerance and error handling program abilities should be verified by simulating the faults in the transmission path.Reproduction of faults during system maintenance is also important to test the stability and reliability of fiber channel system.Therefore,the development of FC-AE(Fibre Channel-Avionics Environment)bus fault simulation device has practical application significance.FC-AE bus fault simulation device realizes the simulation of the fault between two fiber channel nodes.On the basis of detailed analysis of FC-AE protocol,this thesis analyzes necessary fault simulation items of FC-AE bus fault simulation device,and proposes the overall design scheme.The structure adopts the CPCIe(Compact Peripheral Component Interconnect express)portable chassis with turn-down LCD display,uses standard embedded CPCIe computer module as the controller inside the chassis,and develops a fiber channel communication module to realize the fault injection function.The fiber channel communication module communicates with the computer by CPCI bus interface.According to the configuration,FC-AE bus fault simulation could realize three types of data transmission rates 1.0625 Gbps,2.125 Gbps and 4.25 Gbps.This thesis discusses the functions and design methods of FC-AE bus fault simulation device.The firmware design is the core of the fiber channel communication module design.The firmware is divided into the following modules:PCI interface module,high-speed transceiver module and data processing module.The data processing module designs and implements the frame and word trigger and fault injection under 4 sets of trigger conditions.The injection method of fault includes: delete,replace,insert.This thesis introduces the design method of triggering and processing logic in detail.At the same time,this thesis introduces the application method of FPGA high speed transceiver.After fault injection,data is output to NT device by high speed transceiver.In the hardware part,this thesis introduces the design of firmware signal circuit to ensure signal integrity,including the PCB material selection and layout requirements.Meanwhile,this thesis introduces the design of FPGA related circuitand CPCI related circuit.The software part is responsible for configuring the fault injection type and trigger conditions of the fault injection module,and receiving the statistical information generated in the process of fault injection.In order to verify the function of the fault simulation device,this thesis carries out the simulation test first.After that,two sets of test platforms are built for different communication rates.In the test platform,the fault injection test is carried out.The test results show that the FC-AE bus fault simulation device could implement all the functions required.