A Research Of4GS/s Timing Analysis And High-speed Trigger Technology

In the testing of digital systems, when the concerned issues are logical relationship or time relationship between the signals, the universal testing instruments cannot meet the requirements for relatively small number of channels. However, logic analyzer provides a possible solution.As one of the main instruments of the data field testing, the logic analyzer is with many indicators to evaluate its performance, such as channel number, timing analysis of the maximum rate, the state analysis of the maximum rate, trigger mode, the storage capacity et al.Based on the analysis of domestic and foreign logic analyzers, the research contents are concluded. The dissertation discusses the timing analysis and the design of trigger recognition scheme of logic analyzer, and also the circuit of logic analyzer was design.The details are as follows:1) A variety of logic analyzer timing analysis design schemes are put forward. Based on the comparison of each scheme, this dissertation decides to use a serial-to-parallel conversion technique, which uses the peripheral serial-to-parallel conversion chip to decelerate the rate of processing data, and then the data is sent to the FPGA for acquisition and processing. Hardware circuit of this scheme has been designed.2) After analysis of the logic analyzer trigger recognition technique, we proposed the idea of parallel trigger recognition for high-speed sampling scheme, and then designed the FPGA logic circuit about edge, burr, pattern and sequence triggered to achieve the correct trigger.3) We debugged the circuit and tested the functions of trigger recognition module.Finally, a conclusion is given. Some suggestions for improving the performance of logic analyzer are also provided.