Research On Key Technologies Of 5GSPS High Resolution Data Acquisition And Processing

With the rapid development of electronic testing technology,it has become the direction of many engineers to present high-speed electrical signals more accurately and clearly.Therefore,for the acquisition system,the sampling rate and resolution have been the subject of in-depth research.Continuous increase of sampling rate,the pressure means that the interface also in unceasing increase,the traditional high speed parallel an LVDS(low voltage differential signal)standard interface has been increasingly cannot meet the development of the present sampling rate,a series of new interface based on serial architecture and interface agreement arises at the historic moment,and will become the future trend of high speed transmission.Based on the emerging serial architecture,this paper studies the construction of high resolution acquisition system and the design of serial transmission protocol module.The basic technical indicators of the specific acquisition system are as follows: the sampling rate is up to 5GSPS,the vertical resolution is up to 12 bits,and the effective digit is up to 8.8 bits.The key technologies related to acquisition and processing are analyzed in detail.The specific module design and module indicators are shown as follows.1?Research based on JESD204B(JEDEC standard serial protocol)serial transmission protocol under high resolution TIADC(time alternating sampling ADC)acquisition system,analyses its than the traditional advantages of parallel transmission,from the system clock,sampling plan,control module and the receiver of the FPGA(field programmable gate array)were normal,including the realization of the acquisition process and the design process,complete five GSPS normal acquisition of high resolution acquisition system.2?Study the single-channel multi-link synchronization technology and multichannel synchronization technology under JESD204 B serial transmission protocol,analyze the feasibility of synchronization algorithm from the perspective of deterministic delay,deeply analyze the implementation process of serial synchronization,and realize the delay compensation provided by the standard of serial transmission protocol in FPGA.3?The inter-board transmission module based on GTX(Gigabit Transceiver)and the high-speed communication module of Peripheral Component Interconnect Express based on PEX8311 bridge chip were designed,and the actual transmission speed of the custom protocol reached 6.25 Gbps,and the bit error rate was lower than that.4?TIADC error model of the system,using the sine fitting to gain error and offset error estimates,in the presence of undersampling,analysis based on FFT(fast Fourier transform)error estimation methods of spectrum analysis to correct estimation of time error,and using FPGA internal computing unit build adder,multiplier and fractional delay FIR filter to realize the Numbers of the three kinds of error correction,to complete the 8.8 a design of significant digits.5?The high resolution acquisition system and the designed modules were tested in practice.After the test,the construction of the TIADC system was completed correctly,the GTX and PCIe error-free testing was completed,and the three mismatch errors were corrected correctly.