Low-Power Nerve Stimulator Designed For Visual Prosthesis

In this era,we mainly rely on the eyes to obtain information,blindness has brought enormous obstacles to all aspects of people's lives.Furthermore the increase in medical burden and the decline in productivity will cause huge social costs.With the development and progress of various subjects,the nerve repair technology has made us believe there is hope of restoring the visual function of the blind,made the visual prosthesis a research hotspot all over the world.This paper proposes a structure of optic nerve stimulator,completes the design and simulation of the analog circuit,and designs and simulates the layout of some circuits.The optic nerve stimulator designed in this paper includes three parts:stimulation current generation circuit,charge balance circuit and electrode monitoring circuit.Combined with substrate driving technology,the power supply voltage is reduced to 0.9V to achieve low power consumption design.The DAC circuit in the stimulating current generating circuit adopts a segmented current type structure,which realizes a compromise between high matching degree and chip area,and improves the structure of the conventional positive and negative current generating circuit,so as to be used at a low voltage.The circuit is designed and simulated based on SMIC 0.18?m process library.The results show that the stimulation current generation circuit can generate positive and negative bidirectional stimulation currents according to the design requirements,and the pulse width and amplitude of the current pulse can be controlled.The power consumption of the DAC circuit is 0.12mW,and the overall power consumption of the stimulus current generating circuit is about 1.9mW.The two-stage dynamic comparator without static power consumption is used in the charge balancing circuit to correctly judge the state of charge accumulation.The SAR ADC circuit in the electrode monitoring circuit uses a low-energy DAC capacitor network switching method.Compared with the traditional structure switching method,the switching energy consumed by the DAC capacitor network is reduced by 93.74%.The simulation result shows that the input frequency is 53.906.kHz,sampling frequency 200kHz,SNDR is 49.51dB,SFDR is 61.29dB,effective digit is 7.93bit,power consumption is only 20nW.