Research On Package Optimization Design And Parallel Current Balance Of Power Module

Driven by the emerging market of electric vehicles,new energy generation,and smart grid,high-power inverters are required with ratings close to or even beyond 1 MVA with 1200 V or 1700 V devices.Restricted by cost and manufacture quality,semiconductors are usually parallel packaged as multi-chip power modules to meet the high current demand.Considering the multi-chip power module represents a key role in inverter efficiency and reliability,methods from both semiconductor and packaging are addressed to improve the performance of the multi-chip power module.Theoretically,the performance of SiC and GaN devices surpasses that of Si devices regarding switching loss,switching speed and current density with orders of magnitude.However,multi-chip power module packaging becomes a limiting factor in fully realizing these benefits,and thus,it is wise to address optimization design and packaging to ensure the efficient and reliability of large-capacity inverters.Several critical barriers to multi-chip power module packaging need to be solved.First,power module is complex with multi-physics coupling and non-linear semiconductors.From the multi-objective optimization constraction point of view,minimizing inductances and thermomechanical stress constractions are obstacle to provide sufficient lifetime regardless of the inherent CTE-mismatch of the different materials used.With multi-physics objective contradictions,mathematical model of power module is rather difficult to establish.Secondly,designing power electronic circuits to switch currents in the range of several hundred amps within fractions of a microsecond is a demanding task for engineer and requires a sound knowledge how to balance current imbalance between parallel devices.Paralleling of small units helps to minimize stray inductances but unfortunately creating the new task of ensuring proper current sharing.Beside these technical challenges the power electronic designer is more and more faced with cost targets difficult to meet.Further,it is always an important issue in the high power range to allow easy parallel connection since changing to a bigger module is not an option anymore.In views of the above difficulties,several key solutions such as layout optimization design,integration technology and current distribution mathematical model are proposed with the logic of single chip to multi-chip as well as design to implementation.These novel and important conclusions are drawn as follows.(1)First,the coupling principles among electric-thermal-stress multi-physics in power modules,characteristics of parasitics,thermal-resistance,power-cycling and thermal-cycling based life-times are modeled and quantified.To achieve an advanced power package,the trade-off among parasitic inductance,thermal resistance,and reliability are revealed,then a multi-objective optimal model is proposed to balance the electric-thermal-stress trade-off.NSGA-II genetic algorithm is employed to obtain the Pareto-based optimal solutions.According to the multi-objective model,the effect principles of solders,ceramics,and baseplates by using different materials are comprehensively compared.Additionally,the specifications of packaging materials in each layer are represented.Considering the interaction of package and device performance,full Si,hybrid,and full SiC power modules,material principles and manufacturing procedures of wire-bonding power modules were presented step-by-step in this paper.By using the same package and test method,comprehensively comparison and analyses of the studied three power modules on dynamic performance was proposed,which is of reference value for the device selection to meet the requirements of different applications.(2)Secondly,the concept of zero temperature sensitivity switching frequency is proposed,showing an electro-thermal stabilizing mechanism of parallel silicon PiN diodes.Mathematical models are established to analyze reverse recovery of multiple parallel diodes with junction temperature imbalance from 25 to 150 ?C.Experimental result reveals that the imbalance of reverse recovery losses increases exponentially with the junction temperature mismatch.This positive temperature-dependence of switching losses goes against the effect on conduction loss.Therefore,the concept of zero temperature sensitivity switching frequency is proposed to define the maximum switching frequency and avoid thermal overstress,providing a useful tool to evaluate the electro-thermal stability of power modules and optimize the switching frequency or de-rate the power module in converter design.(3)Finally,general mechanism models are proposed to reveal the layout-dominated dynamic current imbalance in the multichip power module.The influence of the layout on the current sharing is comparatively evaluated by power modules with and without Kelvin connections.Considering the dynamic current imbalance,based on a commercial multichip power module,finite element analysis and equivalent electric circuit are utilized to illustrate the impact of Kelvin connection.General mathematical and graphical models are created to address the current sharing of parallel chips affected by networked parasitic impedances.Based on the fabricated power module prototypes,extensive experiments and detailed analyses are presented concerning the current sharing,transient time,and switching loss.It is demonstrated the Kelvin connection can elevate switching speed and reduce switching loss of parallel chips,while its functionality to eliminate dynamic current imbalance depends on the parasitic impedances.Some general design guidelines of multichip power module are presented for current sharing.To achieve satisfactory current sharing,advanced packaging layout by using the optimized chip arrangement and wire interconnection is further needed for the multichip power module.