Design And Implementation Of A Low Power Real-Time Clock

With the rapid development of the IC industry,the design goals of a chip are becoming more and more stringent.In addition to traditional requirements for chip performance and area,chip power consumption is also one of the issues that chip designers must consider today.Furthermore,the wide use of portable electronic devices makes chip at the beginning of the design must take into account the impact of the chip power consumption.As for how to reduce the power consumption of chips,designers have summarized and researched various methods of low power design of chips from different design angles,including system level,structure level,register transfer level,logic level,circuit level or transistor level.Research shows that the higher level of low-power technology has greater impact on chip power consumption,thus the low power design strategy adopted at the system level or structure level usually yields more low-power designs than those at the circuit level or transistor level.Digital real-time clock is one of the most widely used electronic chips.As an always-on cell in the Microcontroller Unit,its main function is to display the current time and alarm reminder.When the system is closed or not working,the module still needs to work normally.At this time,the clock unit is battery powered,so its low power consumption design has high research significance and application value.The goal of this paper is to analyze the components of the chip's power consumption and analyze the low-power design methods that can be used in the various stages of the chip design,and then design an effective way to reduce the power consumption of the digital real-time clock when it is working.The main work of this paper includes the research of pre technical background,code compilation and simulation,code synthesis into gate level circuit,automatic placement and routing,timing and power consumption analysis,and low-power design methods interspersed in the above parts.The low-power design work is mainly reflected in: 1)in the code writing stage,by optimizing the code structure,some unnecessary registers and unnecessary turns in some registers are reduced.2)In the selection of the divider structure,the frequency division method by using the register series mode can greatly reduce the power consumption generated by the transmitted statistics divider.This mode can also reduce the chip area.3)In the circuit,the dynamic power and static power consumption of the circuit are optimized by using multi threshold voltage technology,gated power supply technology and multi power supply voltage technology.By enumerating six different chip design methods,this paper studies the way of chip power optimization.At the end of the article,the power consumption of these chips is characterized by professional power analysis software.Finally,through comparison and analysis,a design method of optimal power consumption in these designs is obtained.