| With the explosive growth of location-based service,one of the effective ways to improve positioning accuracy is to use multi-system navigation satellite receivers,which are mostly used in low-power mobile devices.As an important part of RF receiver,frequency synthesizer has always been a research hotspot for research institutions and companies.Therefore,in-depth study and design of the required frequency synthesizer,in the low power consumption and low noise,support for receiving multiple frequency bands,high-quality signals is a very meaningful work.Considering loop bandwidth and the frequency selection of navigation satellite work,this paper selects the phase-locked loop based fractional-N frequency synthesizer.The mathematical model of the sub-module is analyzed,the linear model of the system is established,the phase noise model of the system can be obtained after the introduction of noise,and the phase transfer function characteristics of each module can be derived to guide the circuit design and the overall phase noise fitting.In view of the characteristics of the navigation satellite receiver,the planning of the fractional-N frequency synthesizer specifications is carried out and the appropriate sub-module scheme is selected to achieve these specifications.Includes the selection of dual-mode voltage-controlled oscillators with a negative resistance structure to achieve wide frequency output range and low phase noise with lower power consumption and low voltage-controlled gain,and a combination of dual-mode pre-divider,pulse-swallowing counter and MASH 1-1-1 to achieve fractional-N Divider with high-speed and wide divide ratio range;select phase frequency detector circuits and programmable charge pump structure for sensitive phase and frequency detection and maintain a stable loop bandwidth when changing the divide ratio and voltage-controlled gain;and automatic frequency band selection circuit selection in closed-loop mode,so as to achieve a reasonable frequency band of the voltage-controlled oscillator when there is a low voltage gain and a higher reference frequency,and a third-order passive low-pass filter is selected to verify the loop stability after determining the loop parameters.After determining the indicators and circuit structure of the specific sub-circuit,this paper adopts the 65nmCMOS process design to realize the dual-mode voltage-controlled oscillator,fractional-N divider,phase frequency detector,charge pump,automatic frequency band selection circuit and loop filter,and the design specifications is basically completed after simulation verification.The output specifications of the voltage-controlled oscillator contains the divide by 2 circuit is divided into two bands,divided into 32 bands covering 1.1GHz to 1.65GHz,the voltage-controlled gain is divided into 22MHz/V and 35MHz/V,and the frequency band covers each other 20%to 30%,phase noise is-96dBc@100KHz.The divide ratio of the fractional divider is 32 to 127,the frequency resolution is 24.8Hz,and the programmable charge pump current is 200uA and 250uA.In this paper,the fractional-N frequency synthesizer for navigation satellite receivers is applied to BDS-3 satellite signal B1C(1575.42MHz).With the reference frequency 26MHz,the integer input of the fractional-N divider is 60 and the input of MASH1-1-1 is 621886(2'b10010111110100111110)After simulation,the loop bandwidth is 100K and the lock time is 30us,including the fine tuning time and the time selected by the automatic frequency band selection circuit,with a power consumption of about 6mW.The simulation obtains the phase noise or noise power spectral density of each module,through its phase noise transfer function,fits in MATLAB to obtain the total phase noise,with in-of-band phase noise-96dBc,with out-of-band phase noise-120dBc@1MHz... |
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