Design Of Signal Processing Platform For Multi-Core DSP Ultra-short Baseline Positioning System

Among all positioning systems,the ultra-short baseline positioning system(USBL)is small,easy to carry and install,and of high positioning accuracy.Therefore,USBL is widely used.Longer-range,higher-precision and multi-functionality are the current development trends of USBL,which puts higher requirements on the performance of the USBL digital signal processing platform(USBL-DSPP).Based on this background,this paper designs a new generation of USBL-DSPP based on TI's latest series of DSP,C667x multi-core DSP.While completing the acquisition,uploading and processing of the response signal from the underwater target,it provides sufficient residual resources for the future research to improve the accuracy,the range,and the target quantity of USBL,and to realize the integration of positioning and communication.In terms of hardware design,the DSP+FPGA architecture is adopted,with a multi-core DSP TMS320C6674 and an EP2S90F780I4N FPGA are used as the core chips,and the corresponding peripheral circuits are designed according to the functions to be realized by the platform.One of the four cores in the multi-core DSP is used as the delay core,and is responsible for extracting the delay information from the collected signal;the other core of the multi-core DSP is used as the main control core,and is responsible for calculating the target coordinates based on the delay information and the GPS compass data,and uploading the target coordinates to the upper computer;the other two cores are reserved for later algorithm expansion.The FPGA is responsible for parameter setting,synchronization signal generation,data acquisition control,serial communication control,and bandpass filtering of sampled data.One piece of ADS8568 is used to collect data;two TL16C754 are used to receive data from the GPS and compasses and commands from the upper computer,and upload the positioning results to the upper computer;one piece of hardware protocol stack chip W5300 is used to realize 100 Mbps network,uploading the original collected data to the upper computer for storage.In terms of software design,firstly,the paper briefly introduces the principle of broadband ultra-short baseline positioning and the FFT method of correlation sequence and envelope,and then introduces the software design of each functional module in detail.The FPGA software design includes system parameter configuration,synchronization signal generation,and bandpass filtering.The Serial Communication Module software design includes initialization of TL16C754 and data transmission and reception.The Original Acquisition Data Upload Module software design is introduced from four parts:W5300 reset,W5300 initialization,SOCKET initialization and acquisition data transmission.The design of the Delay Core Signal Processing software is described in detail in four parts:data reception,signal detection and storage,signal processing and delay result forwarding.In addition,the design of A/D Data Acquisition software and Multi-core DSP Inter-core Communication software is also introduced in detail.In terms of platform debugging,the Data Acquisition Module,the Serial Communication Module,the Original Acquisition Data Upload Module and the Delay Core Signal Processing Module are debugged respectively.The results show that every module can work normally.Finally,the platform is co-tuned in the laboratory,and a signal source is used to simulate the transponder.The platform correctly can correctly calculate out the delay difference.