Research And Design Of SAR ADC In X-ray Detector Readout Circuit

X-ray is an electromagnetic wave with extremely short wavelength,high energy and strong penetrating power discovered by German physicist W.K.Roentgen in 1985.Based on the above characteristics,X-ray detectors have been widely used in medical,industrial,aerospace and other fields.X-ray detectors generally consist of a front-end detection circuit,a signal readout circuit,and a subsequent digital signal processing module.For the front-end column-level readout circuit,it needs to amplify the detected weak signal,reducing noise,performing analog-to-digital conversion and then output.As a bridge between analog and digital signals,the analog-to-digital converter(ADC)plays a key role.For the column-level readout circuit,in order to reduce the non-uniformity between different pixel units,the pixel units in each column need to share an ADC for data conversion.Therefore,the ADC is required to have a certain speed on the basis of low power consumption and small area.Compared with other types of ADCS,the SAR ADC itself does not require linear gain modules.Except for a comparator,the SAR ADC is composed of digital circuits.The SAR ADC has the characteristics of low power consumption and small area.In addition,thanks to the gradual reduction in the size of modern CMOS technology and the application of various high-speed technologies applied to SAR ADC,SAR ADC has also achieved better performance in terms of speed,getting rid of the low speed tag.In this paper,the basic principle of SAR ADC is introduced in detail,and the functions of key modules such as capacitive digital-to-analog converter(C-DAC),high-speed comparator,sampling switch,asynchronous SAR logic and error correction circuit are analyzed.Among them,the sampling switch uses a pre-charging bootstrap switch at the cost of adding a simple clock circuit,which effectively improves the sampling speed and reduces the bootstrap capacitance;The segmented structure is used on the C-DAC to effectively reduce the number of capacitors per unit.At the same time the monotone switching strategy is used to further reduce the number of capacitors and effectively reduce the power consumption.In addition,in order to solve the problem of insufficient C-DAC voltage in medium-high speed SAR ADC,binary correction technology is used to make ADC have certain fault tolerance;On the basis of the single-stage folding comparator,a kind of speed-enhanced comparator is proposed to improve the comparison speed;SAR logic use asynchronous logic,avoiding external high-frequency clock,effectively reducing power consumption and circuit complexity.In addition,it uses TSPC storage unit instead of traditional d-type trigger,effectively saving area and improving the feedback speed from digital circuit to C-DAC;The error correction circuit converts the 14-bit redundant code into the 12-bit binary code and has the overflow judgment function.Based on the Cadence platform,under the SMIC 0.13?m 1P8 M CMOS process,the circuit and layout design of a 12-bit 16 MS / s SAR ADC has been completed.Simulation results show that the signal distortion ratio of the ADC is 68.9 d B,and the integral nonlinearity error of the static characteristics is-0.81/+1.155 LSB,respectively.It satisfies the application of the front-end readout circuit of the X-ray detector.