Design Of Clock Generation Circuits For The Pixellevel Particle Readout Circuit

In order to study the physical properties of unknown particles and energy in micro-structured gas detectors,three-dimensional reconstruction of particle flight trajectories can be performed by extracting time-of-flight information and energy information of particles in the detector of the Pixellevel particle readout circuit.Among them,the accuracy of time measurement determines the accuracy of the vertical axis of particle flight path reconstruction.Therefore,in order to achieve highly accurate time measurement,it is particularly important to introduce a high frequency clock count in the readout circuit.For application in particle readout circuit arrays,the 1GHz phase-locked loop designed in this thesisis mainly used for the generation of high-frequency clock in the readout circuit.It is designed to achieve 1ns Time-to-Digital Converter(TDC)accuracy with the system clock.On the basis of the previous work,the readout circuit was optimized and improved,and the integration of the 1GHz highfrequency clock circuit and the 4×4 readout circuit was completed,realizing a complete 4×4 pixellevel readout circuit.A single phase-locked loop(PLL)generates a stable control voltage,which is supplied to the local oscillator of each pixel in the readout array.The local oscillator is controlled to operate at the target frequency,automatically compensating the frequency fluctuations caused by the supply voltage,process and temperature changes.The phase frequency detector uses a D flip-flop and a NAND gate to form a three-state logic circuit,and minimizes the dead zone under the premise of eliminating the phase dead zone.The charge pump uses a current-steering structure that operates at high speed to reduce the effects of nonideal effects.The low-pass filter uses second-order RC filtering to stabilize the loop while reducing fluctuations in the control voltage.The voltage controlled oscillator is realized with a varactor based ring oscillator,and suppress nonlinearity.The frequency divider is realized with the TSPC D flip-flop.The structure is simple,and the phase noise contribution is small.The rail-to-rail buffer is a closedloop application of a constant-gain two-stage constant transconductance op amp,which has good linearity,large dynamic range of input and output.In this thesis,the circuit is implemented in a 0.18?m CMOS process.The simulation results show that the PLL can be locked to the target frequency at each process corner,achieving a locking range of 0.918GHz~1.105 GHz.At a typical process corner,the local oscillator has a start-up time of 492.9 ps and a duty cycle of 50.32%.The absolute jitter of the PLL is 11.4 ps,and the lock time is approximately 0.5 ?s,consuming a total power dissipation of 1.9 mA ×1.8V.In addition,the layout area of the PLL is approximately 290?m×105?m.Similarly,the post-layout simulation results of the PLL-based TDC readout circuit 4×4 pixel array shows that the time error of TDC is less than 1 ns.The output integrated signal is sampled and read by the analog-to-digital converter,and the voltage accuracy is within 2.5 mV,corresponding to a charge.Accordingly,the resolution is 0.5fC.The individual pixel areas constituting the pixel array are both 250 ?m × 250 ?m.The power consumption is about 1.44 mW,and the total area of the chip of the 4×4 readout array is 1570 ?m × 1730 ?m.